const CacheLinePadSize = 256
+var HWCap uint
+
// bitIsSet reports whether the bit at index is set. The bit index
// is in big endian order, so bit index 0 is the leftmost bit.
func bitIsSet(bits []uint64, index uint) bool {
// vector facilities
vxe facility = 135 // vector-enhancements 1
- // Note: vx and highgprs are excluded because they require
- // kernel support and so must be fetched from HWCAP.
+ // Note: vx requires kernel support
+ // and so must be fetched from HWCAP.
+
+ hwcap_VX = 1 << 11 // vector facility
)
// facilityList contains the result of an STFLE call.
S390X.HasEDDSA = kdsa.Has(eddsaVerifyEd25519, eddsaSignEd25519, eddsaVerifyEd448, eddsaSignEd448)
}
}
+
+ S390X.HasVX = isSet(HWCap, hwcap_VX)
+
if S390X.HasVX {
S390X.HasVXE = facilities.Has(vxe)
}
}
+
+func isSet(hwc uint, value uint) bool {
+ return hwc&value != 0
+}
import "internal/cpu"
-const (
- // bit masks taken from bits/hwcap.h
- _HWCAP_S390_VX = 2048 // vector facility
-)
-
func archauxv(tag, val uintptr) {
switch tag {
- case _AT_HWCAP: // CPU capability bit flags
- cpu.S390X.HasVX = val&_HWCAP_S390_VX != 0
+ case _AT_HWCAP:
+ cpu.HWCap = uint(val)
}
}