cmd/asm/internal/asm: add arm64 end to end tests

Add end to end tests for arm64 to support CL 8405.

There are several instruction forms commented out at the moment
they will be addressed in CL 8405 or later followups.

Change-Id: I6eeeb810c1e03cd49bb3c881bc46a29cdb817822
Reviewed-on: https://go-review.googlesource.com/8631
Reviewed-by: Aram Hăvărneanu <aram@mgk.ro>
Reviewed-by: Rob Pike <r@golang.org>

diff --git a/src/cmd/asm/internal/asm/endtoend_test.go b/src/cmd/asm/internal/asm/endtoend_test.go
index 58c32387c00544333960e4de5f2bb7db4c6cc002..43f11caca0810d23efe5f1b14e8e3b2c39028d30 100644 (file)
--- a/src/cmd/asm/internal/asm/endtoend_test.go
+++ b/src/cmd/asm/internal/asm/endtoend_test.go
@@ -78,6 +78,10 @@ func TestARMEndToEnd(t *testing.T) {
        testEndToEnd(t, "arm")
 }
 
+func TestARM64EndToEnd(t *testing.T) {
+       testEndToEnd(t, "arm64")
+}
+
 func TestAMD64EndToEnd(t *testing.T) {
        testEndToEnd(t, "amd64")
 }

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.out b/src/cmd/asm/internal/asm/testdata/arm64.out
new file mode 100644 (file)
index 0000000..077c562
--- /dev/null
+++ b/src/cmd/asm/internal/asm/testdata/arm64.out
@@ -0,0 +1,46 @@
+5 00001 (testdata/arm64.s:5)   TEXT    foo(SB), 7, $-8
+16 00002 (testdata/arm64.s:16) ADDW    $1, R2, R3
+17 00003 (testdata/arm64.s:17) ADDW    R1, R2, R3
+18 00004 (testdata/arm64.s:18) ADDW    R1, ZR, R3
+19 00005 (testdata/arm64.s:19) ADD     $1, R2, R3
+20 00006 (testdata/arm64.s:20) ADD     R1, R2, R3
+21 00007 (testdata/arm64.s:21) ADD     R1, ZR, R3
+22 00008 (testdata/arm64.s:22) ADD     $1, R2, R3
+32 00009 (testdata/arm64.s:32) ADDW    $1, R2
+33 00010 (testdata/arm64.s:33) ADDW    R1, R2
+34 00011 (testdata/arm64.s:34) ADD     $1, R2
+35 00012 (testdata/arm64.s:35) ADD     R1, R2
+44 00013 (testdata/arm64.s:44) CLSW    R1, R2
+45 00014 (testdata/arm64.s:45) CLS     R1, R2
+54 00015 (testdata/arm64.s:54) MOVW    R1, R2
+55 00016 (testdata/arm64.s:55) MOVW    ZR, R1
+56 00017 (testdata/arm64.s:56) MOVW    R1, ZR
+57 00018 (testdata/arm64.s:57) MOVW    $1, ZR
+58 00019 (testdata/arm64.s:58) MOVW    $1, R1
+59 00020 (testdata/arm64.s:59) MOVW    ZR, (R1)
+60 00021 (testdata/arm64.s:60) MOVD    R1, R2
+61 00022 (testdata/arm64.s:61) MOVD    ZR, R1
+62 00023 (testdata/arm64.s:62) MOVD    $1, ZR
+63 00024 (testdata/arm64.s:63) MOVD    $1, R1
+64 00025 (testdata/arm64.s:64) MOVD    ZR, (R1)
+73 00026 (testdata/arm64.s:73) MOVK    $1, R1
+82 00027 (testdata/arm64.s:82) CALL    28(PC)
+88 00028 (testdata/arm64.s:88) CALL    (R2)
+89 00029 (testdata/arm64.s:89) CALL    foo(SB)
+90 00030 (testdata/arm64.s:90) CALL    bar<>(SB)
+98 00031 (testdata/arm64.s:98) BEQ     32(PC)
+106 00032 (testdata/arm64.s:106)       SVC
+115 00033 (testdata/arm64.s:115)       CMP     $3, R2
+116 00034 (testdata/arm64.s:116)       CMP     R1, R2
+126 00035 (testdata/arm64.s:126)       CBZ     R1
+135 00036 (testdata/arm64.s:135)       CSET    GT, R1
+149 00037 (testdata/arm64.s:149)       CSEL    LT, R1, R2
+166 00038 (testdata/arm64.s:166)       FADDD   $(0.5), F1
+167 00039 (testdata/arm64.s:167)       FADDD   F1, F2
+173 00040 (testdata/arm64.s:173)       FADDD   $(0.69999999999999996), F1, F2
+174 00041 (testdata/arm64.s:174)       FADDD   F1, F2, F3
+226 00042 (testdata/arm64.s:226)       DMB     $1
+235 00043 (testdata/arm64.s:235)       LDAXRW  (R0), R2
+236 00044 (testdata/arm64.s:236)       STLXRW  R1, (R0), R3
+244 00045 (testdata/arm64.s:244)       RET
+252 00046 (testdata/arm64.s:252)       END

diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
new file mode 100644 (file)
index 0000000..6cb0edf
--- /dev/null
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -0,0 +1,252 @@
+// This input was created by taking the instruction productions in
+// the old assembler's (7a's) grammar and hand-writing complete
+// instructions for each rule, to guarantee we cover the same space.
+
+TEXT   foo(SB), 7, $-8
+
+//
+// ADD
+//
+//     LTYPE1 imsr ',' spreg ',' reg
+//     {
+//             outcode($1, &$2, $4, &$6);
+//     }
+// imsr comes from the old 7a, we only support immediates and registers
+// at the moment, no shifted registers.
+       ADDW    $1, R2, R3
+       ADDW    R1, R2, R3
+       ADDW    R1, ZR, R3
+       ADD     $1, R2, R3
+       ADD     R1, R2, R3
+       ADD     R1, ZR, R3
+       ADD     $1, R2, R3
+
+//     LTYPE1 imsr ',' spreg ','
+//     {
+//             outcode($1, &$2, $4, &nullgen);
+//     }
+//     LTYPE1 imsr ',' reg
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+       ADDW    $1, R2
+       ADDW    R1, R2
+       ADD     $1, R2
+       ADD     R1, R2
+
+//
+// CLS
+//
+//     LTYPE2 imsr ',' reg
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+       CLSW    R1, R2
+       CLS     R1, R2
+
+//
+// MOV
+//
+//     LTYPE3 addr ',' addr
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+       MOVW    R1, R2
+       MOVW    ZR, R1
+       MOVW    R1, ZR
+       MOVW    $1, ZR
+       MOVW    $1, R1
+       MOVW    ZR, (R1)
+       MOVD    R1, R2
+       MOVD    ZR, R1
+       MOVD    $1, ZR
+       MOVD    $1, R1
+       MOVD    ZR, (R1)
+
+//
+// MOVK
+//
+//             LMOVK imm ',' reg
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+       MOVK    $1, R1
+
+//
+// B/BL
+//
+//             LTYPE4 comma rel
+//     {
+//             outcode($1, &nullgen, NREG, &$3);
+//     }
+       BL      1(PC)
+
+//             LTYPE4 comma nireg
+//     {
+//             outcode($1, &nullgen, NREG, &$3);
+//     }
+       BL      (R2)
+       BL      foo(SB)
+       BL      bar<>(SB)
+//
+// BEQ
+//
+//             LTYPE5 comma rel
+//     {
+//             outcode($1, &nullgen, NREG, &$3);
+//     }
+       BEQ     1(PC)
+//
+// SVC
+//
+//             LTYPE6
+//     {
+//             outcode($1, &nullgen, NREG, &nullgen);
+//     }
+       SVC
+
+//
+// CMP
+//
+//             LTYPE7 imsr ',' spreg comma
+//     {
+//             outcode($1, &$2, $4, &nullgen);
+//     }
+       CMP     $3, R2
+       CMP     R1, R2
+
+//
+// CBZ
+//
+//             LTYPE8 reg ',' rel
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+again:
+       CBZ     R1, again
+
+//
+// CSET
+//
+//             LTYPER cond ',' reg
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+       CSET    GT, R1
+//
+// CSEL/CINC/CNEG/CINV
+//
+//             LTYPES cond ',' reg ',' reg ',' reg
+//     {
+//             outgcode($1, &$2, $6.reg, &$4, &$8);
+//     }
+//     CSEL    LT, R1, R2, ZR
+
+//             LTYPES cond ',' reg ',' reg
+//     {
+//             outcode($1, &$2, $4.reg, &$6);
+//     }
+       CSEL    LT, R1, R2
+//
+// CCMN
+//
+//             LTYPEU cond ',' imsr ',' reg ',' imm comma
+//     {
+//             outgcode($1, &$2, $6.reg, &$4, &$8);
+//     }
+//     CCMN    MI, $1, R1, $4
+
+//
+// FADDD
+//
+//             LTYPEK frcon ',' freg
+//     {
+//             outcode($1, &$2, NREG, &$4);
+//     }
+       FADDD   $0.5, F1
+       FADDD   F1, F2
+
+//             LTYPEK frcon ',' freg ',' freg
+//     {
+//             outcode($1, &$2, $4.reg, &$6);
+//     }
+       FADDD   $0.7, F1, F2
+       FADDD   F1, F2, F3
+
+//
+// FCMP
+//
+//             LTYPEL frcon ',' freg comma
+//     {
+//             outcode($1, &$2, $4.reg, &nullgen);
+//     }
+//     FCMP    $0.2, F1
+//     FCMP    F1, F2
+
+//
+// FCCMP
+//
+//             LTYPEF cond ',' freg ',' freg ',' imm comma
+//     {
+//             outgcode($1, &$2, $6.reg, &$4, &$8);
+//     }
+//     FCCMP   LT, F1, F2, $1
+
+//
+// FMULA
+//
+//             LTYPE9 freg ',' freg ',' freg ',' freg comma
+//     {
+//             outgcode($1, &$2, $4.reg, &$6, &$8);
+//     }
+//     FMULA   F1, F2, F3, F4
+
+//
+// FCSEL
+//
+//             LFCSEL cond ',' freg ',' freg ',' freg
+//     {
+//             outgcode($1, &$2, $6.reg, &$4, &$8);
+//     }
+//
+// MADD Rn,Rm,Ra,Rd
+//
+//             LTYPEM reg ',' reg ',' sreg ',' reg
+//     {
+//             outgcode($1, &$2, $6, &$4, &$8);
+//     }
+//     MADD    R1, R2, R3, R4
+
+// DMB, HINT
+//
+//             LDMB imm
+//     {
+//             outcode($1, &$2, NREG, &nullgen);
+//     }
+       DMB     $1
+
+//
+// STXR
+//
+//             LSTXR reg ',' addr ',' reg
+//     {
+//             outtcode($1, &$2, &$4, &$6);
+//     }
+       LDAXRW  (R0), R2
+       STLXRW  R1, (R0), R3
+
+// RET
+//
+//             LTYPEA comma
+//     {
+//             outcode($1, &nullgen, NREG, &nullgen);
+//     }
+       RET
+
+// END
+//
+//     LTYPEE comma
+//     {
+//             outcode($1, &nullgen, NREG, &nullgen);
+//     }
+       END