cmd/compile: remove output registers limit for MUL/DIV on loong64

This limitation exists on MIPS platform, but not on loong64.

Change-Id: I14bb3ec6895a8f7850873c171e1756843ffea72e
Reviewed-on: https://go-review.googlesource.com/c/go/+/449395
Reviewed-by: Michael Knyszek <mknyszek@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Run-TryBot: Wayne Zuo <wdvxdr@golangcn.org>
Reviewed-by: David Chase <drchase@google.com>

diff --git a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
index 3b9fc7c8713d3bd9c74352ee39effc54c33d322c..22a83fb300a110b24241614eac996951d33a0619 100644 (file)
--- a/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
+++ b/src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
@@ -142,7 +142,7 @@ func init() {
                gp11      = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
                gp11sp    = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
                gp21      = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
-               gpmuldiv  = regInfo{inputs: []regMask{gps, gps}, outputs: []regMask{buildReg("R17"), buildReg("R18")}}
+               gp22      = regInfo{inputs: []regMask{gps, gps}, outputs: []regMask{gp, gp}}
                gpload    = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
                gpstore   = regInfo{inputs: []regMask{gpspsbg, gpg}}
                gpstore0  = regInfo{inputs: []regMask{gpspsbg}}
@@ -163,10 +163,10 @@ func init() {
                {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"},                      // arg0 - arg1
                {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"},   // arg0 - auxInt
 
-               {name: "MULV", argLength: 2, reg: gpmuldiv, commutative: true, typ: "(Int64,Int64)"},    // arg0 * arg1, signed
-               {name: "MULVU", argLength: 2, reg: gpmuldiv, commutative: true, typ: "(UInt64,UInt64)"}, // arg0 * arg1, unsigned
-               {name: "DIVV", argLength: 2, reg: gpmuldiv, typ: "(Int64,Int64)"},                       // arg0 / arg1, signed
-               {name: "DIVVU", argLength: 2, reg: gpmuldiv, typ: "(UInt64,UInt64)"},                    // arg0 / arg1, unsigned
+               {name: "MULV", argLength: 2, reg: gp22, resultNotInArgs: true, commutative: true, typ: "(Int64,Int64)"},    // arg0 * arg1, signed
+               {name: "MULVU", argLength: 2, reg: gp22, resultNotInArgs: true, commutative: true, typ: "(UInt64,UInt64)"}, // arg0 * arg1, unsigned
+               {name: "DIVV", argLength: 2, reg: gp22, resultNotInArgs: true, typ: "(Int64,Int64)"},                       // arg0 / arg1, signed
+               {name: "DIVVU", argLength: 2, reg: gp22, resultNotInArgs: true, typ: "(UInt64,UInt64)"},                    // arg0 / arg1, unsigned
 
                {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1
                {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1

diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go
index fe57305bc6efca4ac72a684c7fee9a2457c79fb4..d84bc279a4abeb4a13b4585c77e7bc6abfeca21e 100644 (file)
--- a/src/cmd/compile/internal/ssa/opGen.go
+++ b/src/cmd/compile/internal/ssa/opGen.go
@@ -22912,60 +22912,64 @@ var opcodeTable = [...]opInfo{
                },
        },
        {
-               name:        "MULV",
-               argLen:      2,
-               commutative: true,
+               name:            "MULV",
+               argLen:          2,
+               commutative:     true,
+               resultNotInArgs: true,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                                {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 65536},  // R17
-                               {1, 131072}, // R18
+                               {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:        "MULVU",
-               argLen:      2,
-               commutative: true,
+               name:            "MULVU",
+               argLen:          2,
+               commutative:     true,
+               resultNotInArgs: true,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                                {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 65536},  // R17
-                               {1, 131072}, // R18
+                               {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "DIVV",
-               argLen: 2,
+               name:            "DIVV",
+               argLen:          2,
+               resultNotInArgs: true,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                                {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 65536},  // R17
-                               {1, 131072}, // R18
+                               {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },
        {
-               name:   "DIVVU",
-               argLen: 2,
+               name:            "DIVVU",
+               argLen:          2,
+               resultNotInArgs: true,
                reg: regInfo{
                        inputs: []inputInfo{
                                {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                                {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31
                        },
                        outputs: []outputInfo{
-                               {0, 65536},  // R17
-                               {1, 131072}, // R18
+                               {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
+                               {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31
                        },
                },
        },