From: limeidan Date: Thu, 11 Jan 2024 07:04:45 +0000 (+0800) Subject: cmd/internal/obj/loong64, cmd/asm: remove invalid optab items X-Git-Tag: go1.24rc1~1368 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=33b247437f871a850a778dc214245ba5d1a0c9a0;p=gostls13.git cmd/internal/obj/loong64, cmd/asm: remove invalid optab items Cases 27 and 28 are used to handle floating point operations, MOVW is usually used for integer processing, and, in two cases there is code like this: a :=AMOVF if p.As == AMOVD { a=AMOVD } This means that MOVW was eventually replaced by MOVF, so removed MOVW from cases 27 and 28. Change-Id: Ib438febab88058e98b569e0dfe70b8610668ee31 Reviewed-on: https://go-review.googlesource.com/c/go/+/565622 LUCI-TryBot-Result: Go LUCI Reviewed-by: Qiqi Huang Auto-Submit: abner chenc Reviewed-by: sophie zhao Reviewed-by: abner chenc Reviewed-by: Michael Knyszek Reviewed-by: Cherry Mui --- diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index a45ef88150..0f451a9050 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -124,16 +124,12 @@ lable2: BNE R4, R0, 1(PC) // 80040044 BNE R0, R4, 1(PC) // 80040044 BLTU R4, 1(PC) // 80040068 - MOVW y+8(FP), F4 // 6440002b MOVF y+8(FP), F4 // 6440002b MOVD y+8(FP), F4 // 6440802b - MOVW 1(F5), F4 // a404002b MOVF 1(F5), F4 // a404002b MOVD 1(F5), F4 // a404802b - MOVW F4, result+16(FP) // 6460402b MOVF F4, result+16(FP) // 6460402b MOVD F4, result+16(FP) // 6460c02b - MOVW F4, 1(F5) // a404402b MOVF F4, 1(F5) // a404402b MOVD F4, 1(F5) // a404c02b MOVW R4, F5 // 85a41401 diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc3.s b/src/cmd/asm/internal/asm/testdata/loong64enc3.s index eceb0d71d0..2600884309 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc3.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc3.s @@ -64,28 +64,20 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVV 4096(R5), R4 // 3e000014de971000c403c028 MOVB 4096(R5), R4 // 3e000014de971000c4030028 MOVBU 4096(R5), R4 // 3e000014de971000c403002a - MOVW y+65540(FP), F4 // 1e020014de8f1000c433002b MOVF y+65540(FP), F4 // 1e020014de8f1000c433002b MOVD y+65540(FP), F4 // 1e020014de8f1000c433802b - MOVW y+4097(FP), F4 // 3e000014de8f1000c427002b MOVF y+4097(FP), F4 // 3e000014de8f1000c427002b MOVD y+4097(FP), F4 // 3e000014de8f1000c427802b - MOVW 65536(R5), F4 // 1e020014de971000c403002b MOVF 65536(R5), F4 // 1e020014de971000c403002b MOVD 65536(R5), F4 // 1e020014de971000c403802b - MOVW 4096(R5), F4 // 3e000014de971000c403002b MOVF 4096(R5), F4 // 3e000014de971000c403002b MOVD 4096(R5), F4 // 3e000014de971000c403802b - MOVW F4, result+65540(FP) // 1e020014de8f1000c433402b MOVF F4, result+65540(FP) // 1e020014de8f1000c433402b MOVD F4, result+65540(FP) // 1e020014de8f1000c433c02b - MOVW F4, result+4097(FP) // 3e000014de8f1000c427402b MOVF F4, result+4097(FP) // 3e000014de8f1000c427402b MOVD F4, result+4097(FP) // 3e000014de8f1000c427c02b - MOVW F4, 65536(R5) // 1e020014de971000c403402b MOVF F4, 65536(R5) // 1e020014de971000c403402b MOVD F4, 65536(R5) // 1e020014de971000c403c02b - MOVW F4, 4096(R5) // 3e000014de971000c403402b MOVF F4, 4096(R5) // 3e000014de971000c403402b MOVD F4, 4096(R5) // 3e000014de971000c403c02b diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go index 8325cbf905..fbfa7024d6 100644 --- a/src/cmd/internal/obj/loong64/asm.go +++ b/src/cmd/internal/obj/loong64/asm.go @@ -155,12 +155,9 @@ var optab = []Optab{ {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, {ASC, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0}, {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0}, @@ -184,12 +181,9 @@ var optab = []Optab{ {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, {AMOVBU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0}, {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, - {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0}, {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0}, @@ -202,7 +196,6 @@ var optab = []Optab{ {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0}, {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0}, {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP}, - {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP}, {AMOVV, C_LECON, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP}, {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 26, 12, REGSP, 0}, @@ -280,49 +273,37 @@ var optab = []Optab{ {AMOVW, C_SEXT, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, 0, 0}, {AMOVF, C_SEXT, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, 0, 0}, {AMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, 0, 0}, - {AMOVW, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, REGSP, 0}, {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, REGSP, 0}, {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, REGSP, 0}, - {AMOVW, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, REGZERO, 0}, {AMOVF, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, REGZERO, 0}, {AMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 27, 4, REGZERO, 0}, {AMOVW, C_LEXT, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, 0, 0}, {AMOVF, C_LEXT, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, 0, 0}, {AMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, 0, 0}, - {AMOVW, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, REGSP, 0}, {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, REGSP, 0}, {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, REGSP, 0}, - {AMOVW, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, REGZERO, 0}, {AMOVF, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, REGZERO, 0}, {AMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 27, 12, REGZERO, 0}, {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, - {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, - {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0}, {AMOVW, C_FREG, C_NONE, C_NONE, C_SEXT, C_NONE, 28, 4, 0, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_SEXT, C_NONE, 28, 4, 0, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, C_NONE, 28, 4, 0, 0}, - {AMOVW, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 28, 4, REGSP, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 28, 4, REGSP, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 28, 4, REGSP, 0}, - {AMOVW, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 28, 4, REGZERO, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 28, 4, REGZERO, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 28, 4, REGZERO, 0}, {AMOVW, C_FREG, C_NONE, C_NONE, C_LEXT, C_NONE, 28, 12, 0, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_LEXT, C_NONE, 28, 12, 0, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, C_NONE, 28, 12, 0, 0}, - {AMOVW, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 28, 12, REGSP, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 28, 12, REGSP, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 28, 12, REGSP, 0}, - {AMOVW, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 28, 12, REGZERO, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 28, 12, REGZERO, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 28, 12, REGZERO, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, - {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0}, {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0}, @@ -1602,18 +1583,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { if r == 0 { r = int(o.param) } - a := -AMOVF - if p.As == AMOVD { - a = -AMOVD - } switch o.size { case 12: o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP)) o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP)) - o3 = OP_12IRR(c.opirr(a), uint32(v), uint32(REGTMP), uint32(p.To.Reg)) + o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg)) case 4: - o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg)) + o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg)) } case 28: // mov fr,[sl]ext/auto/oreg @@ -1622,18 +1599,14 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { if r == 0 { r = int(o.param) } - a := AMOVF - if p.As == AMOVD { - a = AMOVD - } switch o.size { case 12: o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP)) o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP)) - o3 = OP_12IRR(c.opirr(a), uint32(v), uint32(REGTMP), uint32(p.From.Reg)) + o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg)) case 4: - o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.From.Reg)) + o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg)) } case 29: // fcmp.cond.x fj, fk, fcc