From: Cherry Zhang Date: Fri, 2 Nov 2018 20:51:14 +0000 (-0400) Subject: cmd/asm: rename R18 to R18_PLATFORM on ARM64 X-Git-Tag: go1.12beta1~468 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=35c05542938416cde6a366505c24568ea5ccd98e;p=gostls13.git cmd/asm: rename R18 to R18_PLATFORM on ARM64 In ARM64 ABI, R18 is the "platform register", the use of which is OS specific. The OS could choose to reserve this register. In practice, it seems fine to use R18 on Linux but not on darwin (iOS). Rename R18 to R18_PLATFORM to prevent accidental use. There is no R18 usage within the standard library (besides tests, which are updated). Fixes #26110 Change-Id: Icef7b9549e2049db1df307a0180a3c90a12d7a84 Reviewed-on: https://go-review.googlesource.com/c/147218 Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot Reviewed-by: Brad Fitzpatrick --- diff --git a/doc/asm.html b/doc/asm.html index f2f8fad576..debb1e2fc6 100644 --- a/doc/asm.html +++ b/doc/asm.html @@ -740,6 +740,7 @@ The ARM64 port is in an experimental state.

R18 is the "platform register", reserved on the Apple platform. +To prevent accidental misuse, the register is named R18_PLATFORM. R27 and R28 are reserved by the compiler and linker. R29 is the frame pointer. R30 is the link register. diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go index ecea6ba97d..eaa5cb8958 100644 --- a/src/cmd/asm/internal/arch/arch.go +++ b/src/cmd/asm/internal/arch/arch.go @@ -258,6 +258,9 @@ func archArm64() *Arch { for i := arm64.REG_R0; i <= arm64.REG_R31; i++ { register[obj.Rconv(i)] = int16(i) } + // Rename R18 to R18_PLATFORM to avoid accidental use. + register["R18_PLATFORM"] = register["R18"] + delete(register, "R18") for i := arm64.REG_F0; i <= arm64.REG_F31; i++ { register[obj.Rconv(i)] = int16(i) } diff --git a/src/cmd/asm/internal/asm/operand_test.go b/src/cmd/asm/internal/asm/operand_test.go index df60b71ebd..69393b6b20 100644 --- a/src/cmd/asm/internal/asm/operand_test.go +++ b/src/cmd/asm/internal/asm/operand_test.go @@ -607,6 +607,7 @@ var arm64OperandTests = []operandTest{ {"R0", "R0"}, {"R10", "R10"}, {"R11", "R11"}, + {"R18_PLATFORM", "R18"}, {"$4503601774854144.0", "$(4503601774854144.0)"}, {"$runtime·badsystemstack(SB)", "$runtime.badsystemstack(SB)"}, {"ZR", "ZR"}, diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index b851ba411e..a577c4da9d 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -47,8 +47,8 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 ADD R2.SXTX<<1, RSP, RSP // ffe7228b ADD ZR.SXTX<<1, R2, R3 // 43e43f8b ADDW R2.SXTW, R10, R12 // 4cc1220b - ADD R18.UXTX, R14, R17 // d161328b - ADDSW R18.UXTW, R14, R17 // d141322b + ADD R19.UXTX, R14, R17 // d161338b + ADDSW R19.UXTW, R14, R17 // d141332b ADDS R12.SXTX, R3, R1 // 61e02cab SUB R19.UXTH<<4, R2, R21 // 553033cb SUBW R1.UXTX<<1, R3, R2 // 6264214b @@ -144,7 +144,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 MOVD (R2)(R6.SXTW), R4 // 44c866f8 MOVD (R3)(R6), R5 // MOVD (R3)(R6*1), R5 // 656866f8 MOVD (R2)(R6), R4 // MOVD (R2)(R6*1), R4 // 446866f8 - MOVWU (R19)(R18<<2), R18 // 727a72b8 + MOVWU (R19)(R20<<2), R20 // 747a74b8 MOVD (R2)(R6<<3), R4 // 447866f8 MOVD (R3)(R7.SXTX<<3), R8 // 68f867f8 MOVWU (R5)(R4.UXTW), R10 // aa4864b8 @@ -154,7 +154,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 MOVHU (R1)(R2<<1), R5 // 25786278 MOVB (R9)(R3.UXTW), R6 // 2649a338 MOVB (R10)(R6), R15 // MOVB (R10)(R6*1), R15 // 4f69a638 - MOVH (R5)(R7.SXTX<<1), R18 // b2f8a778 + MOVH (R5)(R7.SXTX<<1), R19 // b3f8a778 MOVH (R8)(R4<<1), R10 // 0a79a478 MOVW (R9)(R8.SXTW<<2), R19 // 33d9a8b8 MOVW (R1)(R4.SXTX), R11 // 2be8a4b8 diff --git a/src/cmd/asm/internal/asm/testdata/arm64enc.s b/src/cmd/asm/internal/asm/testdata/arm64enc.s index 432ab74493..a2850e2e46 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64enc.s +++ b/src/cmd/asm/internal/asm/testdata/arm64enc.s @@ -56,7 +56,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 BFXILW $3, R27, $23, R14 // 6e670333 BFXIL $26, R8, $16, R20 // 14a55ab3 BICW R7@>15, R5, R16 // b03ce70a - BIC R12@>13, R12, R18 // 9235ec8a + BIC R12@>13, R12, R19 // 9335ec8a BICSW R25->20, R3, R20 // 7450b96a BICS R19->12, R1, R23 // 3730b3ea BICS R19, R1, R23 // 370033ea @@ -76,7 +76,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 CCMN LE, R30, R12, $6 // c6d34cba CCMPW VS, R29, $15, $7 // a76b4f7a CCMP LE, R7, $19, $3 // e3d853fa - CCMPW HS, R18, R6, $0 // 4022467a + CCMPW HS, R19, R6, $0 // 6022467a CCMP LT, R30, R6, $7 // c7b346fa CCMN MI, ZR, R1, $4 // e44341ba CSINCW HS, ZR, R27, R14 // ee279b1a @@ -118,7 +118,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 CRC32H R3, R21, R27 // bb46c31a CRC32W R22, R30, R9 // c94bd61a CRC32X R20, R4, R15 // 8f4cd49a - CRC32CB R18, R27, R22 // 7653d21a + CRC32CB R19, R27, R22 // 7653d31a CRC32CH R21, R0, R20 // 1454d51a CRC32CW R9, R3, R21 // 7558c91a CRC32CX R11, R0, R24 // 185ccb9a @@ -133,7 +133,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 CSINVW AL, R23, R21, R5 // e5e2955a CSINV LO, R2, R11, R14 // 4e308bda CSNEGW HS, R16, R29, R10 // 0a269d5a - CSNEG NE, R21, R18, R11 // ab1692da + CSNEG NE, R21, R19, R11 // ab1693da //TODO DC DCPS1 $11378 // 418ea5d4 DCPS2 $10699 // 6239a5d4 @@ -185,23 +185,23 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 MOVBU.P 42(R2), R12 // 4ca44238 MOVBU.W -27(R2), R14 // 4e5c5e38 MOVBU 2916(R24), R3 // 03936d39 - MOVBU (R18)(R14<<0), R23 // 577a6e38 + MOVBU (R19)(R14<<0), R23 // 777a6e38 MOVBU (R2)(R8.SXTX), R19 // 53e86838 MOVBU (R27)(R23), R14 // MOVBU (R27)(R23*1), R14 // 6e6b7738 MOVHU.P 107(R14), R13 // cdb54678 MOVHU.W 192(R3), R2 // 620c4c78 - MOVHU 6844(R4), R18 // 92787579 + MOVHU 6844(R4), R19 // 93787579 MOVHU (R5)(R25.SXTW), R15 // afc87978 - //TODO MOVBW.P 77(R18), R11 // 4bd6c438 + //TODO MOVBW.P 77(R19), R11 // 6bd6c438 MOVB.P 36(RSP), R27 // fb478238 - //TODO MOVBW.W -57(R18), R13 // 4d7edc38 + //TODO MOVBW.W -57(R19), R13 // 6d7edc38 MOVB.W -178(R16), R24 // 18ee9438 //TODO MOVBW 430(R8), R22 // 16b9c639 MOVB 997(R9), R23 // 37958f39 //TODO MOVBW (R2<<1)(R21), R15 // af7ae238 //TODO MOVBW (R26)(R0), R21 // 1568fa38 MOVB (R5)(R15), R16 // MOVB (R5)(R15*1), R16 // b068af38 - MOVB (R18)(R26.SXTW), R19 // 53caba38 + MOVB (R19)(R26.SXTW), R19 // 73caba38 MOVB (R29)(R30), R14 // MOVB (R29)(R30*1), R14 // ae6bbe38 //TODO MOVHW.P 218(R22), R25 // d9a6cd78 MOVH.P 179(R23), R5 // e5368b78 @@ -212,7 +212,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 //TODO MOVHW (R22)(R24.SXTX), R4 // c4eaf878 MOVH (R26)(R30.UXTW<<1), ZR // 5f5bbe78 MOVW.P -58(R16), R2 // 02669cb8 - MOVW.W -216(R18), R8 // 488e92b8 + MOVW.W -216(R19), R8 // 688e92b8 MOVW 4764(R23), R10 // ea9e92b9 MOVW (R8)(R3.UXTW), R17 // 1149a3b8 //TODO LDTR -0x1e(R3), R4 // 64285eb8 @@ -297,7 +297,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 RET // c0035fd6 REVW R8, R10 // 0a09c05a REV R1, R2 // 220cc0da - REV16W R21, R18 // b206c05a + REV16W R21, R19 // b306c05a REV16 R25, R4 // 2407c0da REV32 R27, R21 // 750bc0da EXTRW $27, R4, R25, R19 // 336f8413 @@ -308,7 +308,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 ROR R0, R23, R2 // e22ec09a SBCW R4, R8, R24 // 1801045a SBC R25, R10, R26 // 5a0119da - SBCSW R27, R18, R18 // 52021b7a + SBCSW R27, R19, R19 // 73021b7a SBCS R5, R9, R5 // 250105fa SBFIZW $9, R10, $18, R22 // 56451713 SBFIZ $6, R11, $15, R20 // 74397a93 @@ -337,7 +337,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 //TODO STNPW 44(R1), R3, R10 // 2a8c0528 //TODO STNP 0x108(R3), ZR, R7 // 67fc10a8 LDP.P -384(R3), (R22, R26) // 7668e8a8 - LDP.W 280(R8), (R18, R11) // 12add1a9 + LDP.W 280(R8), (R19, R11) // 13add1a9 STP.P (R22, R27), 352(R0) // 166c96a8 STP.W (R17, R11), 96(R8) // 112d86a9 MOVW.P R20, -28(R1) // 34441eb8 @@ -360,22 +360,22 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 MOVB R2, (R29)(R26) // MOVB R2, (R29)(R26*1) // a26b3a38 MOVH R11, -80(R23) // eb021b78 MOVH R11, (R27)(R14.SXTW<<1) // 6bdb2e78 - MOVB R18, (R0)(R4) // MOVB R18, (R0)(R4*1) // 12682438 + MOVB R19, (R0)(R4) // MOVB R19, (R0)(R4*1) // 13682438 MOVB R1, (R6)(R4) // MOVB R1, (R6)(R4*1) // c1682438 MOVH R3, (R11)(R13<<1) // 63792d78 //TODO STTR 55(R4), R29 // 9d7803b8 //TODO STTR 124(R5), R25 // b9c807f8 //TODO STTRB -28(R23), R16 // f04a1e38 - //TODO STTRH 9(R10), R18 // 52990078 + //TODO STTRH 9(R10), R19 // 53990078 STXP (R1, R2), (R3), R10 // 61082ac8 STXP (R1, R2), (RSP), R10 // e10b2ac8 STXPW (R1, R2), (R3), R10 // 61082a88 STXPW (R1, R2), (RSP), R10 // e10b2a88 - STXRW R2, (R19), R18 // 627e1288 + STXRW R2, (R19), R20 // 627e1488 STXR R15, (R21), R13 // af7e0dc8 STXRB R7, (R9), R24 // 277d1808 STXRH R12, (R3), R8 // 6c7c0848 - SUBW R20.UXTW<<2, R23, R18 // f24a344b + SUBW R20.UXTW<<2, R23, R19 // f34a344b SUB R5.SXTW<<2, R1, R26 // 3ac825cb SUB $(1923<<12), R4, R27 // SUB $7876608, R4, R27 // 9b0c5ed1 SUBW $(1923<<12), R4, R27 // SUBW $7876608, R4, R27 // 9b0c5e51 @@ -410,12 +410,12 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 UBFXW $3, R7, $20, R15 // ef580353 UBFX $33, R17, $25, R5 // 25e661d3 UDIVW R8, R21, R15 // af0ac81a - UDIV R2, R18, R21 // 550ac29a + UDIV R2, R19, R21 // 750ac29a UMADDL R0, R20, R17, R17 // 3152a09b UMSUBL R22, R4, R3, R7 // 6790b69b - UMNEGL R3, R18, R1 // 41fea39b + UMNEGL R3, R19, R1 // 61fea39b UMULH R24, R20, R24 // 987ed89b - UMULL R18, R22, R19 // d37eb29b + UMULL R19, R22, R19 // d37eb39b UXTBW R2, R6 // 461c0053 UXTHW R7, R20 // f43c0053 VCNT V0.B8, V0.B8 // 0058200e @@ -471,7 +471,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 //TODO FCVTAS F27, R7 // 6703241e //TODO FCVTAS F19, R26 // 7a02249e //TODO FCVTAS F4, R0 // 8000641e - //TODO FCVTAS F3, R18 // 7200649e + //TODO FCVTAS F3, R19 // 7300649e //TODO FCVTAU F18, F28 // 5cca217e //TODO VFCVTAU V30.S4, V27.S4 // dbcb216e //TODO FCVTAU F0, R2 // 0200251e @@ -482,16 +482,16 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 //TODO VFCVTL2 V15.H8, V25.S4 // f979214e //TODO FCVTMS F21, F28 // bcba215e //TODO VFCVTMS V5.D2, V2.D2 // a2b8614e - //TODO FCVTMS F31, R18 // f203301e + //TODO FCVTMS F31, R19 // f303301e //TODO FCVTMS F23, R16 // f002309e //TODO FCVTMS F16, R22 // 1602701e //TODO FCVTMS F14, R19 // d301709e //TODO FCVTMU F14, F8 // c8b9217e //TODO VFCVTMU V7.D2, V1.D2 // e1b8616e //TODO FCVTMU F2, R0 // 4000311e - //TODO FCVTMU F23, R18 // f202319e + //TODO FCVTMU F23, R19 // f302319e //TODO FCVTMU F16, R17 // 1102711e - //TODO FCVTMU F12, R18 // 9201719e + //TODO FCVTMU F12, R19 // 9301719e //TODO VFCVTN V23.D2, V26.S2 // fa6a610e //TODO VFCVTN2 V2.D2, V31.S4 // 5f68614e //TODO FCVTNS F3, F27 // 7ba8215e @@ -540,7 +540,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 //TODO FCVTZU $14, F24, R20 // 14cb191e //TODO FCVTZU $6, F25, R17 // 31eb199e //TODO FCVTZU $5, F17, R10 // 2aee591e - //TODO FCVTZU $6, F7, R18 // f2e8599e + //TODO FCVTZU $6, F7, R19 // f3e8599e FCVTZUSW F2, R9 // 4900391e FCVTZUS F12, R29 // 9d01399e FCVTZUDW F27, R22 // 7603791e @@ -682,11 +682,11 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 VLD1.P (R19)(R4), [V24.B8, V25.B8] // VLD1.P (R19)(R4*1), [V24.B8, V25.B8] // 78a2c40c VLD1.P (R20)(R8), [V7.H8, V8.H8, V9.H8] // VLD1.P (R20)(R8*1), [V7.H8, V8.H8, V9.H8] // 8766c84c VLD1.P 32(R30), [V5.B8, V6.B8, V7.B8, V8.B8] // c523df0c - VLD1 (R18), V14.B[15] // 4e1e404d + VLD1 (R19), V14.B[15] // 6e1e404d VLD1 (R29), V0.H[1] // a04b400d VLD1 (R27), V2.S[0] // 6283400d VLD1 (R21), V5.D[1] // a586404d - VLD1.P 1(R18), V10.B[14] // 4a1adf4d + VLD1.P 1(R19), V10.B[14] // 6a1adf4d VLD1.P (R3)(R14), V16.B[11] // VLD1.P (R3)(R14*1), V16.B[11] // 700cce4d VLD1.P 2(R1), V28.H[2] // 3c50df0d VLD1.P (R13)(R20), V9.H[2] // VLD1.P (R13)(R20*1), V9.H[2] // a951d40d diff --git a/src/cmd/internal/obj/arm64/doc.go b/src/cmd/internal/obj/arm64/doc.go index 845fb22817..7fb129989b 100644 --- a/src/cmd/internal/obj/arm64/doc.go +++ b/src/cmd/internal/obj/arm64/doc.go @@ -89,7 +89,7 @@ such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1. Examples: MOVD R29, 384(R19) <=> str x29, [x19,#384] MOVB.P R30, 30(R4) <=> strb w30, [x4],#30 - STLRH R21, (R18) <=> stlrh w21, [x18] + STLRH R21, (R19) <=> stlrh w21, [x19] (2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL , , , @@ -127,7 +127,7 @@ such as str, stur, strb, sturb, strh, sturh stlr, stlrb. stlrh, st1. Examples: CCMN VS, R13, R22, $10 <=> ccmn x13, x22, #0xa, vs - CCMPW HS, R18, R14, $11 <=> ccmp w18, w14, #0xb, cs + CCMPW HS, R19, R14, $11 <=> ccmp w19, w14, #0xb, cs (9) CSEL, CSELW, CSNEG, CSNEGW, CSINC, CSINCW , , , ; FCSELD, FCSELS , , , @@ -144,12 +144,12 @@ FCSELD, FCSELS , , , Examples: STLXR ZR, (R15), R16 <=> stlxr w16, xzr, [x15] - STXRB R9, (R21), R18 <=> stxrb w18, w9, [x21] + STXRB R9, (R21), R19 <=> stxrb w19, w9, [x21] (12) STLXP, STLXPW, STXP, STXPW (, ), (), Examples: - STLXP (R17, R18), (R4), R5 <=> stlxp w5, x17, x18, [x4] + STLXP (R17, R19), (R4), R5 <=> stlxp w5, x17, x19, [x4] STXPW (R30, R25), (R22), R13 <=> stxp w13, w30, w25, [x22] 2. Expressions for special arguments. @@ -173,7 +173,7 @@ Extended registers are written as {.{<<}}. can be UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW or SXTX. Examples: - ADDS R18.UXTB<<4, R9, R26 <=> adds x26, x9, w18, uxtb #4 + ADDS R19.UXTB<<4, R9, R26 <=> adds x26, x9, w19, uxtb #4 ADDSW R14.SXTX, R14, R6 <=> adds w6, w14, w14, sxtx Memory references: [{,#0}] is written as (Rn|RSP), a base register and an immediate