From: Michael Munday Date: Tue, 27 Sep 2016 14:29:43 +0000 (-0400) Subject: cmd/asm: fix parsing of the s390x VLE{G,F,H,B} instructions X-Git-Tag: go1.8beta1~1139 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=413f1ef4de98f2e98853c3753f785871bfc32e5d;p=gostls13.git cmd/asm: fix parsing of the s390x VLE{G,F,H,B} instructions This commit makes the assembler frontend reorder the operands so that they are in the order the backend expects. The index should be first for consistency with the other vector instructions. Before this commit no operand order would have been accepted so this isn't a breaking change. Change-Id: I188d57eeb338d27fa1fa6845de0d6d1521b7a6c3 Reviewed-on: https://go-review.googlesource.com/29855 Run-TryBot: Michael Munday TryBot-Result: Gobot Gobot Reviewed-by: Bill O'Farrell Reviewed-by: Brad Fitzpatrick --- diff --git a/src/cmd/asm/internal/arch/s390x.go b/src/cmd/asm/internal/arch/s390x.go index 244758df5f..4110b43ebf 100644 --- a/src/cmd/asm/internal/arch/s390x.go +++ b/src/cmd/asm/internal/arch/s390x.go @@ -112,6 +112,8 @@ func IsS390xWithIndex(op obj.As) bool { return true case s390x.AVLEIG, s390x.AVLEIF, s390x.AVLEIH, s390x.AVLEIB: return true + case s390x.AVLEG, s390x.AVLEF, s390x.AVLEH, s390x.AVLEB: + return true case s390x.AVPDI: return true } diff --git a/src/cmd/asm/internal/asm/testdata/s390x.s b/src/cmd/asm/internal/asm/testdata/s390x.s index be31221d00..5fc7a8e9b5 100644 --- a/src/cmd/asm/internal/asm/testdata/s390x.s +++ b/src/cmd/asm/internal/asm/testdata/s390x.s @@ -257,6 +257,11 @@ TEXT main·foo(SB),7,$16-0 // TEXT main.foo(SB), 7, $16-0 WFMSDB V2, V25, V24, V31 // WFMSDB V25, V24, V2, V31 // e7f298038b8e VPERM V31, V0, V2, V3 // VPERM V0, V2, V31, V3 // e73f0000248c VPDI $1, V2, V31, V1 // VPDI V2, V31, $1, V1 // e712f0001284 + VLEG $1, (R3), V1 // VLEG (R3), $1, V1 // e71030001002 + VLEF $2, (R0), V31 // VLEF (R0), $2, V31 // e7f000002803 + VLEH $3, (R12), V16 // VLEH (R12), $3, V16 // e700c0003801 + VLEB $15, 4095(R9), V15 // VLEB 4095(R9), $15, V15 // e7f09ffff000 + RET