From: Shenghou Ma Date: Fri, 3 Apr 2015 08:37:18 +0000 (-0400) Subject: cmd/internal/obj/arm64, cmd/internal/ld, cmd/7l: remove absolute addressing in .text X-Git-Tag: go1.5beta1~1257 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=6e3a2a3f9fcd476a50ec75f7dd2db7adfe12ab57;p=gostls13.git cmd/internal/obj/arm64, cmd/internal/ld, cmd/7l: remove absolute addressing in .text This CL introduces R_ADDRARM64, which is similar to R_ADDRPOWER. Fixes #10112. Change-Id: I309e3df7608b9eef9339196fdc50dedf5f9439f1 Reviewed-on: https://go-review.googlesource.com/8438 Reviewed-by: Aram Hăvărneanu Reviewed-by: David Crawshaw --- diff --git a/src/cmd/7l/asm.go b/src/cmd/7l/asm.go index 379e9837b6..525ccc660b 100644 --- a/src/cmd/7l/asm.go +++ b/src/cmd/7l/asm.go @@ -33,6 +33,7 @@ package main import ( "cmd/internal/ld" "cmd/internal/obj" + "encoding/binary" "fmt" "log" ) @@ -83,6 +84,13 @@ func elfreloc1(r *ld.Reloc, sectoff int64) int { return -1 } + case ld.R_ADDRARM64: + // two relocations: R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADD_ABS_LO12_NC + ld.Thearch.Vput(ld.R_AARCH64_ADR_PREL_PG_HI21 | uint64(elfsym)<<32) + ld.Thearch.Vput(uint64(r.Xadd)) + ld.Thearch.Vput(uint64(sectoff + 4)) + ld.Thearch.Vput(ld.R_AARCH64_ADD_ABS_LO12_NC | uint64(elfsym)<<32) + case ld.R_CALLARM64: if r.Siz != 4 { return -1 @@ -110,6 +118,36 @@ func archreloc(r *ld.Reloc, s *ld.LSym, val *int64) int { default: return -1 + case ld.R_ADDRARM64: + r.Done = 0 + + // the first instruction is always at the lower address, this is endian neutral; + // but note that o0 and o1 should still use the target endian. + o0 := ld.Thelinkarch.ByteOrder.Uint32(s.P[r.Off : r.Off+4]) + o1 := ld.Thelinkarch.ByteOrder.Uint32(s.P[r.Off+4 : r.Off+8]) + + // when laid out, the instruction order must always be o1, o2. + if ld.Ctxt.Arch.ByteOrder == binary.BigEndian { + *val = int64(o0)<<32 | int64(o1) + } else { + *val = int64(o1)<<32 | int64(o0) + } + + // set up addend for eventual relocation via outer symbol. + rs := r.Sym + r.Xadd = r.Add + for rs.Outer != nil { + r.Xadd += ld.Symaddr(rs) - ld.Symaddr(rs.Outer) + rs = rs.Outer + } + + if rs.Type != ld.SHOSTOBJ && rs.Sect == nil { + ld.Diag("missing section for %s", rs.Name) + } + r.Xsym = rs + + return 0 + case ld.R_CALLARM64: r.Done = 0 r.Xsym = r.Sym @@ -129,6 +167,28 @@ func archreloc(r *ld.Reloc, s *ld.LSym, val *int64) int { *val = ld.Symaddr(r.Sym) + r.Add - ld.Symaddr(ld.Linklookup(ld.Ctxt, ".got", 0)) return 0 + case ld.R_ADDRARM64: + t := ld.Symaddr(r.Sym) + r.Add - ((s.Value + int64(r.Off)) &^ 0xfff) + if t >= 1<<32 || t < -1<<32 { + ld.Diag("program too large, address relocation distance = %d", t) + } + + // the first instruction is always at the lower address, this is endian neutral; + // but note that o0 and o1 should still use the target endian. + o0 := ld.Thelinkarch.ByteOrder.Uint32(s.P[r.Off : r.Off+4]) + o1 := ld.Thelinkarch.ByteOrder.Uint32(s.P[r.Off+4 : r.Off+8]) + + o0 |= (uint32((t>>12)&3) << 29) | (uint32((t>>12>>2)&0x7ffff) << 5) + o1 |= uint32(t&0xfff) << 10 + + // when laid out, the instruction order must always be o1, o2. + if ld.Ctxt.Arch.ByteOrder == binary.BigEndian { + *val = int64(o0)<<32 | int64(o1) + } else { + *val = int64(o1)<<32 | int64(o0) + } + return 0 + case ld.R_CALLARM64: *val = int64((0xfc000000 & uint32(r.Add)) | uint32((ld.Symaddr(r.Sym)+r.Add*4-(s.Value+int64(r.Off)))/4)) return 0 diff --git a/src/cmd/7l/obj.go b/src/cmd/7l/obj.go index 35a0fa8f1c..c6ea541552 100644 --- a/src/cmd/7l/obj.go +++ b/src/cmd/7l/obj.go @@ -119,8 +119,7 @@ func archinit() { ld.INITRND = 4096 } - case ld.Hlinux: /* ppc64 elf */ - ld.Debug['d'] = 1 // TODO(aram): dynamic linking is not supported yet. + case ld.Hlinux: /* arm64 elf */ ld.Elfinit() ld.HEADR = ld.ELFRESERVE if ld.INITTEXT == -1 { diff --git a/src/cmd/internal/ld/elf.go b/src/cmd/internal/ld/elf.go index 86a2aa501e..f932164b47 100644 --- a/src/cmd/internal/ld/elf.go +++ b/src/cmd/internal/ld/elf.go @@ -320,283 +320,285 @@ const ( * Relocation types. */ const ( - R_X86_64_NONE = 0 - R_X86_64_64 = 1 - R_X86_64_PC32 = 2 - R_X86_64_GOT32 = 3 - R_X86_64_PLT32 = 4 - R_X86_64_COPY = 5 - R_X86_64_GLOB_DAT = 6 - R_X86_64_JMP_SLOT = 7 - R_X86_64_RELATIVE = 8 - R_X86_64_GOTPCREL = 9 - R_X86_64_32 = 10 - R_X86_64_32S = 11 - R_X86_64_16 = 12 - R_X86_64_PC16 = 13 - R_X86_64_8 = 14 - R_X86_64_PC8 = 15 - R_X86_64_DTPMOD64 = 16 - R_X86_64_DTPOFF64 = 17 - R_X86_64_TPOFF64 = 18 - R_X86_64_TLSGD = 19 - R_X86_64_TLSLD = 20 - R_X86_64_DTPOFF32 = 21 - R_X86_64_GOTTPOFF = 22 - R_X86_64_TPOFF32 = 23 - R_X86_64_COUNT = 24 - R_AARCH64_ABS64 = 257 - R_AARCH64_ABS32 = 258 - R_AARCH64_CALL26 = 283 - R_ALPHA_NONE = 0 - R_ALPHA_REFLONG = 1 - R_ALPHA_REFQUAD = 2 - R_ALPHA_GPREL32 = 3 - R_ALPHA_LITERAL = 4 - R_ALPHA_LITUSE = 5 - R_ALPHA_GPDISP = 6 - R_ALPHA_BRADDR = 7 - R_ALPHA_HINT = 8 - R_ALPHA_SREL16 = 9 - R_ALPHA_SREL32 = 10 - R_ALPHA_SREL64 = 11 - R_ALPHA_OP_PUSH = 12 - R_ALPHA_OP_STORE = 13 - R_ALPHA_OP_PSUB = 14 - R_ALPHA_OP_PRSHIFT = 15 - R_ALPHA_GPVALUE = 16 - R_ALPHA_GPRELHIGH = 17 - R_ALPHA_GPRELLOW = 18 - R_ALPHA_IMMED_GP_16 = 19 - R_ALPHA_IMMED_GP_HI32 = 20 - R_ALPHA_IMMED_SCN_HI32 = 21 - R_ALPHA_IMMED_BR_HI32 = 22 - R_ALPHA_IMMED_LO32 = 23 - R_ALPHA_COPY = 24 - R_ALPHA_GLOB_DAT = 25 - R_ALPHA_JMP_SLOT = 26 - R_ALPHA_RELATIVE = 27 - R_ALPHA_COUNT = 28 - R_ARM_NONE = 0 - R_ARM_PC24 = 1 - R_ARM_ABS32 = 2 - R_ARM_REL32 = 3 - R_ARM_PC13 = 4 - R_ARM_ABS16 = 5 - R_ARM_ABS12 = 6 - R_ARM_THM_ABS5 = 7 - R_ARM_ABS8 = 8 - R_ARM_SBREL32 = 9 - R_ARM_THM_PC22 = 10 - R_ARM_THM_PC8 = 11 - R_ARM_AMP_VCALL9 = 12 - R_ARM_SWI24 = 13 - R_ARM_THM_SWI8 = 14 - R_ARM_XPC25 = 15 - R_ARM_THM_XPC22 = 16 - R_ARM_COPY = 20 - R_ARM_GLOB_DAT = 21 - R_ARM_JUMP_SLOT = 22 - R_ARM_RELATIVE = 23 - R_ARM_GOTOFF = 24 - R_ARM_GOTPC = 25 - R_ARM_GOT32 = 26 - R_ARM_PLT32 = 27 - R_ARM_CALL = 28 - R_ARM_JUMP24 = 29 - R_ARM_V4BX = 40 - R_ARM_GOT_PREL = 96 - R_ARM_GNU_VTENTRY = 100 - R_ARM_GNU_VTINHERIT = 101 - R_ARM_TLS_IE32 = 107 - R_ARM_TLS_LE32 = 108 - R_ARM_RSBREL32 = 250 - R_ARM_THM_RPC22 = 251 - R_ARM_RREL32 = 252 - R_ARM_RABS32 = 253 - R_ARM_RPC24 = 254 - R_ARM_RBASE = 255 - R_ARM_COUNT = 38 - R_386_NONE = 0 - R_386_32 = 1 - R_386_PC32 = 2 - R_386_GOT32 = 3 - R_386_PLT32 = 4 - R_386_COPY = 5 - R_386_GLOB_DAT = 6 - R_386_JMP_SLOT = 7 - R_386_RELATIVE = 8 - R_386_GOTOFF = 9 - R_386_GOTPC = 10 - R_386_TLS_TPOFF = 14 - R_386_TLS_IE = 15 - R_386_TLS_GOTIE = 16 - R_386_TLS_LE = 17 - R_386_TLS_GD = 18 - R_386_TLS_LDM = 19 - R_386_TLS_GD_32 = 24 - R_386_TLS_GD_PUSH = 25 - R_386_TLS_GD_CALL = 26 - R_386_TLS_GD_POP = 27 - R_386_TLS_LDM_32 = 28 - R_386_TLS_LDM_PUSH = 29 - R_386_TLS_LDM_CALL = 30 - R_386_TLS_LDM_POP = 31 - R_386_TLS_LDO_32 = 32 - R_386_TLS_IE_32 = 33 - R_386_TLS_LE_32 = 34 - R_386_TLS_DTPMOD32 = 35 - R_386_TLS_DTPOFF32 = 36 - R_386_TLS_TPOFF32 = 37 - R_386_COUNT = 38 - R_PPC_NONE = 0 - R_PPC_ADDR32 = 1 - R_PPC_ADDR24 = 2 - R_PPC_ADDR16 = 3 - R_PPC_ADDR16_LO = 4 - R_PPC_ADDR16_HI = 5 - R_PPC_ADDR16_HA = 6 - R_PPC_ADDR14 = 7 - R_PPC_ADDR14_BRTAKEN = 8 - R_PPC_ADDR14_BRNTAKEN = 9 - R_PPC_REL24 = 10 - R_PPC_REL14 = 11 - R_PPC_REL14_BRTAKEN = 12 - R_PPC_REL14_BRNTAKEN = 13 - R_PPC_GOT16 = 14 - R_PPC_GOT16_LO = 15 - R_PPC_GOT16_HI = 16 - R_PPC_GOT16_HA = 17 - R_PPC_PLTREL24 = 18 - R_PPC_COPY = 19 - R_PPC_GLOB_DAT = 20 - R_PPC_JMP_SLOT = 21 - R_PPC_RELATIVE = 22 - R_PPC_LOCAL24PC = 23 - R_PPC_UADDR32 = 24 - R_PPC_UADDR16 = 25 - R_PPC_REL32 = 26 - R_PPC_PLT32 = 27 - R_PPC_PLTREL32 = 28 - R_PPC_PLT16_LO = 29 - R_PPC_PLT16_HI = 30 - R_PPC_PLT16_HA = 31 - R_PPC_SDAREL16 = 32 - R_PPC_SECTOFF = 33 - R_PPC_SECTOFF_LO = 34 - R_PPC_SECTOFF_HI = 35 - R_PPC_SECTOFF_HA = 36 - R_PPC_COUNT = 37 - R_PPC_TLS = 67 - R_PPC_DTPMOD32 = 68 - R_PPC_TPREL16 = 69 - R_PPC_TPREL16_LO = 70 - R_PPC_TPREL16_HI = 71 - R_PPC_TPREL16_HA = 72 - R_PPC_TPREL32 = 73 - R_PPC_DTPREL16 = 74 - R_PPC_DTPREL16_LO = 75 - R_PPC_DTPREL16_HI = 76 - R_PPC_DTPREL16_HA = 77 - R_PPC_DTPREL32 = 78 - R_PPC_GOT_TLSGD16 = 79 - R_PPC_GOT_TLSGD16_LO = 80 - R_PPC_GOT_TLSGD16_HI = 81 - R_PPC_GOT_TLSGD16_HA = 82 - R_PPC_GOT_TLSLD16 = 83 - R_PPC_GOT_TLSLD16_LO = 84 - R_PPC_GOT_TLSLD16_HI = 85 - R_PPC_GOT_TLSLD16_HA = 86 - R_PPC_GOT_TPREL16 = 87 - R_PPC_GOT_TPREL16_LO = 88 - R_PPC_GOT_TPREL16_HI = 89 - R_PPC_GOT_TPREL16_HA = 90 - R_PPC_EMB_NADDR32 = 101 - R_PPC_EMB_NADDR16 = 102 - R_PPC_EMB_NADDR16_LO = 103 - R_PPC_EMB_NADDR16_HI = 104 - R_PPC_EMB_NADDR16_HA = 105 - R_PPC_EMB_SDAI16 = 106 - R_PPC_EMB_SDA2I16 = 107 - R_PPC_EMB_SDA2REL = 108 - R_PPC_EMB_SDA21 = 109 - R_PPC_EMB_MRKREF = 110 - R_PPC_EMB_RELSEC16 = 111 - R_PPC_EMB_RELST_LO = 112 - R_PPC_EMB_RELST_HI = 113 - R_PPC_EMB_RELST_HA = 114 - R_PPC_EMB_BIT_FLD = 115 - R_PPC_EMB_RELSDA = 116 - R_PPC_EMB_COUNT = R_PPC_EMB_RELSDA - R_PPC_EMB_NADDR32 + 1 - R_PPC64_REL24 = R_PPC_REL24 - R_PPC64_JMP_SLOT = R_PPC_JMP_SLOT - R_PPC64_ADDR64 = 38 - R_PPC64_TOC16 = 47 - R_PPC64_TOC16_LO = 48 - R_PPC64_TOC16_HI = 49 - R_PPC64_TOC16_HA = 50 - R_PPC64_TOC16_DS = 63 - R_PPC64_TOC16_LO_DS = 64 - R_PPC64_REL16_LO = 250 - R_PPC64_REL16_HI = 251 - R_PPC64_REL16_HA = 252 - R_SPARC_NONE = 0 - R_SPARC_8 = 1 - R_SPARC_16 = 2 - R_SPARC_32 = 3 - R_SPARC_DISP8 = 4 - R_SPARC_DISP16 = 5 - R_SPARC_DISP32 = 6 - R_SPARC_WDISP30 = 7 - R_SPARC_WDISP22 = 8 - R_SPARC_HI22 = 9 - R_SPARC_22 = 10 - R_SPARC_13 = 11 - R_SPARC_LO10 = 12 - R_SPARC_GOT10 = 13 - R_SPARC_GOT13 = 14 - R_SPARC_GOT22 = 15 - R_SPARC_PC10 = 16 - R_SPARC_PC22 = 17 - R_SPARC_WPLT30 = 18 - R_SPARC_COPY = 19 - R_SPARC_GLOB_DAT = 20 - R_SPARC_JMP_SLOT = 21 - R_SPARC_RELATIVE = 22 - R_SPARC_UA32 = 23 - R_SPARC_PLT32 = 24 - R_SPARC_HIPLT22 = 25 - R_SPARC_LOPLT10 = 26 - R_SPARC_PCPLT32 = 27 - R_SPARC_PCPLT22 = 28 - R_SPARC_PCPLT10 = 29 - R_SPARC_10 = 30 - R_SPARC_11 = 31 - R_SPARC_64 = 32 - R_SPARC_OLO10 = 33 - R_SPARC_HH22 = 34 - R_SPARC_HM10 = 35 - R_SPARC_LM22 = 36 - R_SPARC_PC_HH22 = 37 - R_SPARC_PC_HM10 = 38 - R_SPARC_PC_LM22 = 39 - R_SPARC_WDISP16 = 40 - R_SPARC_WDISP19 = 41 - R_SPARC_GLOB_JMP = 42 - R_SPARC_7 = 43 - R_SPARC_5 = 44 - R_SPARC_6 = 45 - R_SPARC_DISP64 = 46 - R_SPARC_PLT64 = 47 - R_SPARC_HIX22 = 48 - R_SPARC_LOX10 = 49 - R_SPARC_H44 = 50 - R_SPARC_M44 = 51 - R_SPARC_L44 = 52 - R_SPARC_REGISTER = 53 - R_SPARC_UA64 = 54 - R_SPARC_UA16 = 55 - ARM_MAGIC_TRAMP_NUMBER = 0x5c000003 + R_X86_64_NONE = 0 + R_X86_64_64 = 1 + R_X86_64_PC32 = 2 + R_X86_64_GOT32 = 3 + R_X86_64_PLT32 = 4 + R_X86_64_COPY = 5 + R_X86_64_GLOB_DAT = 6 + R_X86_64_JMP_SLOT = 7 + R_X86_64_RELATIVE = 8 + R_X86_64_GOTPCREL = 9 + R_X86_64_32 = 10 + R_X86_64_32S = 11 + R_X86_64_16 = 12 + R_X86_64_PC16 = 13 + R_X86_64_8 = 14 + R_X86_64_PC8 = 15 + R_X86_64_DTPMOD64 = 16 + R_X86_64_DTPOFF64 = 17 + R_X86_64_TPOFF64 = 18 + R_X86_64_TLSGD = 19 + R_X86_64_TLSLD = 20 + R_X86_64_DTPOFF32 = 21 + R_X86_64_GOTTPOFF = 22 + R_X86_64_TPOFF32 = 23 + R_X86_64_COUNT = 24 + R_AARCH64_ABS64 = 257 + R_AARCH64_ABS32 = 258 + R_AARCH64_CALL26 = 283 + R_AARCH64_ADR_PREL_PG_HI21 = 275 + R_AARCH64_ADD_ABS_LO12_NC = 277 + R_ALPHA_NONE = 0 + R_ALPHA_REFLONG = 1 + R_ALPHA_REFQUAD = 2 + R_ALPHA_GPREL32 = 3 + R_ALPHA_LITERAL = 4 + R_ALPHA_LITUSE = 5 + R_ALPHA_GPDISP = 6 + R_ALPHA_BRADDR = 7 + R_ALPHA_HINT = 8 + R_ALPHA_SREL16 = 9 + R_ALPHA_SREL32 = 10 + R_ALPHA_SREL64 = 11 + R_ALPHA_OP_PUSH = 12 + R_ALPHA_OP_STORE = 13 + R_ALPHA_OP_PSUB = 14 + R_ALPHA_OP_PRSHIFT = 15 + R_ALPHA_GPVALUE = 16 + R_ALPHA_GPRELHIGH = 17 + R_ALPHA_GPRELLOW = 18 + R_ALPHA_IMMED_GP_16 = 19 + R_ALPHA_IMMED_GP_HI32 = 20 + R_ALPHA_IMMED_SCN_HI32 = 21 + R_ALPHA_IMMED_BR_HI32 = 22 + R_ALPHA_IMMED_LO32 = 23 + R_ALPHA_COPY = 24 + R_ALPHA_GLOB_DAT = 25 + R_ALPHA_JMP_SLOT = 26 + R_ALPHA_RELATIVE = 27 + R_ALPHA_COUNT = 28 + R_ARM_NONE = 0 + R_ARM_PC24 = 1 + R_ARM_ABS32 = 2 + R_ARM_REL32 = 3 + R_ARM_PC13 = 4 + R_ARM_ABS16 = 5 + R_ARM_ABS12 = 6 + R_ARM_THM_ABS5 = 7 + R_ARM_ABS8 = 8 + R_ARM_SBREL32 = 9 + R_ARM_THM_PC22 = 10 + R_ARM_THM_PC8 = 11 + R_ARM_AMP_VCALL9 = 12 + R_ARM_SWI24 = 13 + R_ARM_THM_SWI8 = 14 + R_ARM_XPC25 = 15 + R_ARM_THM_XPC22 = 16 + R_ARM_COPY = 20 + R_ARM_GLOB_DAT = 21 + R_ARM_JUMP_SLOT = 22 + R_ARM_RELATIVE = 23 + R_ARM_GOTOFF = 24 + R_ARM_GOTPC = 25 + R_ARM_GOT32 = 26 + R_ARM_PLT32 = 27 + R_ARM_CALL = 28 + R_ARM_JUMP24 = 29 + R_ARM_V4BX = 40 + R_ARM_GOT_PREL = 96 + R_ARM_GNU_VTENTRY = 100 + R_ARM_GNU_VTINHERIT = 101 + R_ARM_TLS_IE32 = 107 + R_ARM_TLS_LE32 = 108 + R_ARM_RSBREL32 = 250 + R_ARM_THM_RPC22 = 251 + R_ARM_RREL32 = 252 + R_ARM_RABS32 = 253 + R_ARM_RPC24 = 254 + R_ARM_RBASE = 255 + R_ARM_COUNT = 38 + R_386_NONE = 0 + R_386_32 = 1 + R_386_PC32 = 2 + R_386_GOT32 = 3 + R_386_PLT32 = 4 + R_386_COPY = 5 + R_386_GLOB_DAT = 6 + R_386_JMP_SLOT = 7 + R_386_RELATIVE = 8 + R_386_GOTOFF = 9 + R_386_GOTPC = 10 + R_386_TLS_TPOFF = 14 + R_386_TLS_IE = 15 + R_386_TLS_GOTIE = 16 + R_386_TLS_LE = 17 + R_386_TLS_GD = 18 + R_386_TLS_LDM = 19 + R_386_TLS_GD_32 = 24 + R_386_TLS_GD_PUSH = 25 + R_386_TLS_GD_CALL = 26 + R_386_TLS_GD_POP = 27 + R_386_TLS_LDM_32 = 28 + R_386_TLS_LDM_PUSH = 29 + R_386_TLS_LDM_CALL = 30 + R_386_TLS_LDM_POP = 31 + R_386_TLS_LDO_32 = 32 + R_386_TLS_IE_32 = 33 + R_386_TLS_LE_32 = 34 + R_386_TLS_DTPMOD32 = 35 + R_386_TLS_DTPOFF32 = 36 + R_386_TLS_TPOFF32 = 37 + R_386_COUNT = 38 + R_PPC_NONE = 0 + R_PPC_ADDR32 = 1 + R_PPC_ADDR24 = 2 + R_PPC_ADDR16 = 3 + R_PPC_ADDR16_LO = 4 + R_PPC_ADDR16_HI = 5 + R_PPC_ADDR16_HA = 6 + R_PPC_ADDR14 = 7 + R_PPC_ADDR14_BRTAKEN = 8 + R_PPC_ADDR14_BRNTAKEN = 9 + R_PPC_REL24 = 10 + R_PPC_REL14 = 11 + R_PPC_REL14_BRTAKEN = 12 + R_PPC_REL14_BRNTAKEN = 13 + R_PPC_GOT16 = 14 + R_PPC_GOT16_LO = 15 + R_PPC_GOT16_HI = 16 + R_PPC_GOT16_HA = 17 + R_PPC_PLTREL24 = 18 + R_PPC_COPY = 19 + R_PPC_GLOB_DAT = 20 + R_PPC_JMP_SLOT = 21 + R_PPC_RELATIVE = 22 + R_PPC_LOCAL24PC = 23 + R_PPC_UADDR32 = 24 + R_PPC_UADDR16 = 25 + R_PPC_REL32 = 26 + R_PPC_PLT32 = 27 + R_PPC_PLTREL32 = 28 + R_PPC_PLT16_LO = 29 + R_PPC_PLT16_HI = 30 + R_PPC_PLT16_HA = 31 + R_PPC_SDAREL16 = 32 + R_PPC_SECTOFF = 33 + R_PPC_SECTOFF_LO = 34 + R_PPC_SECTOFF_HI = 35 + R_PPC_SECTOFF_HA = 36 + R_PPC_COUNT = 37 + R_PPC_TLS = 67 + R_PPC_DTPMOD32 = 68 + R_PPC_TPREL16 = 69 + R_PPC_TPREL16_LO = 70 + R_PPC_TPREL16_HI = 71 + R_PPC_TPREL16_HA = 72 + R_PPC_TPREL32 = 73 + R_PPC_DTPREL16 = 74 + R_PPC_DTPREL16_LO = 75 + R_PPC_DTPREL16_HI = 76 + R_PPC_DTPREL16_HA = 77 + R_PPC_DTPREL32 = 78 + R_PPC_GOT_TLSGD16 = 79 + R_PPC_GOT_TLSGD16_LO = 80 + R_PPC_GOT_TLSGD16_HI = 81 + R_PPC_GOT_TLSGD16_HA = 82 + R_PPC_GOT_TLSLD16 = 83 + R_PPC_GOT_TLSLD16_LO = 84 + R_PPC_GOT_TLSLD16_HI = 85 + R_PPC_GOT_TLSLD16_HA = 86 + R_PPC_GOT_TPREL16 = 87 + R_PPC_GOT_TPREL16_LO = 88 + R_PPC_GOT_TPREL16_HI = 89 + R_PPC_GOT_TPREL16_HA = 90 + R_PPC_EMB_NADDR32 = 101 + R_PPC_EMB_NADDR16 = 102 + R_PPC_EMB_NADDR16_LO = 103 + R_PPC_EMB_NADDR16_HI = 104 + R_PPC_EMB_NADDR16_HA = 105 + R_PPC_EMB_SDAI16 = 106 + R_PPC_EMB_SDA2I16 = 107 + R_PPC_EMB_SDA2REL = 108 + R_PPC_EMB_SDA21 = 109 + R_PPC_EMB_MRKREF = 110 + R_PPC_EMB_RELSEC16 = 111 + R_PPC_EMB_RELST_LO = 112 + R_PPC_EMB_RELST_HI = 113 + R_PPC_EMB_RELST_HA = 114 + R_PPC_EMB_BIT_FLD = 115 + R_PPC_EMB_RELSDA = 116 + R_PPC_EMB_COUNT = R_PPC_EMB_RELSDA - R_PPC_EMB_NADDR32 + 1 + R_PPC64_REL24 = R_PPC_REL24 + R_PPC64_JMP_SLOT = R_PPC_JMP_SLOT + R_PPC64_ADDR64 = 38 + R_PPC64_TOC16 = 47 + R_PPC64_TOC16_LO = 48 + R_PPC64_TOC16_HI = 49 + R_PPC64_TOC16_HA = 50 + R_PPC64_TOC16_DS = 63 + R_PPC64_TOC16_LO_DS = 64 + R_PPC64_REL16_LO = 250 + R_PPC64_REL16_HI = 251 + R_PPC64_REL16_HA = 252 + R_SPARC_NONE = 0 + R_SPARC_8 = 1 + R_SPARC_16 = 2 + R_SPARC_32 = 3 + R_SPARC_DISP8 = 4 + R_SPARC_DISP16 = 5 + R_SPARC_DISP32 = 6 + R_SPARC_WDISP30 = 7 + R_SPARC_WDISP22 = 8 + R_SPARC_HI22 = 9 + R_SPARC_22 = 10 + R_SPARC_13 = 11 + R_SPARC_LO10 = 12 + R_SPARC_GOT10 = 13 + R_SPARC_GOT13 = 14 + R_SPARC_GOT22 = 15 + R_SPARC_PC10 = 16 + R_SPARC_PC22 = 17 + R_SPARC_WPLT30 = 18 + R_SPARC_COPY = 19 + R_SPARC_GLOB_DAT = 20 + R_SPARC_JMP_SLOT = 21 + R_SPARC_RELATIVE = 22 + R_SPARC_UA32 = 23 + R_SPARC_PLT32 = 24 + R_SPARC_HIPLT22 = 25 + R_SPARC_LOPLT10 = 26 + R_SPARC_PCPLT32 = 27 + R_SPARC_PCPLT22 = 28 + R_SPARC_PCPLT10 = 29 + R_SPARC_10 = 30 + R_SPARC_11 = 31 + R_SPARC_64 = 32 + R_SPARC_OLO10 = 33 + R_SPARC_HH22 = 34 + R_SPARC_HM10 = 35 + R_SPARC_LM22 = 36 + R_SPARC_PC_HH22 = 37 + R_SPARC_PC_HM10 = 38 + R_SPARC_PC_LM22 = 39 + R_SPARC_WDISP16 = 40 + R_SPARC_WDISP19 = 41 + R_SPARC_GLOB_JMP = 42 + R_SPARC_7 = 43 + R_SPARC_5 = 44 + R_SPARC_6 = 45 + R_SPARC_DISP64 = 46 + R_SPARC_PLT64 = 47 + R_SPARC_HIX22 = 48 + R_SPARC_LOX10 = 49 + R_SPARC_H44 = 50 + R_SPARC_M44 = 51 + R_SPARC_L44 = 52 + R_SPARC_REGISTER = 53 + R_SPARC_UA64 = 54 + R_SPARC_UA16 = 55 + ARM_MAGIC_TRAMP_NUMBER = 0x5c000003 ) /* diff --git a/src/cmd/internal/ld/link.go b/src/cmd/internal/ld/link.go index a5624ed3c5..0a63567dd1 100644 --- a/src/cmd/internal/ld/link.go +++ b/src/cmd/internal/ld/link.go @@ -216,6 +216,7 @@ const ( const ( R_ADDR = 1 + iota R_ADDRPOWER + R_ADDRARM64 R_SIZE R_CALL R_CALLARM diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go index e35a99efae..66780eb7c4 100644 --- a/src/cmd/internal/obj/arm64/asm7.go +++ b/src/cmd/internal/obj/arm64/asm7.go @@ -258,17 +258,19 @@ var optab = []Optab{ {AWORD, C_NONE, C_NONE, C_LEXT, 14, 4, 0, 0, 0}, {AWORD, C_NONE, C_NONE, C_ADDR, 14, 4, 0, 0, 0}, {AMOVW, C_VCON, C_NONE, C_REG, 12, 4, 0, LFROM, 0}, + {AMOVW, C_VCONADDR, C_NONE, C_REG, 68, 8, 0, 0, 0}, {AMOVD, C_VCON, C_NONE, C_REG, 12, 4, 0, LFROM, 0}, - {AMOVB, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AMOVBU, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AMOVH, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AMOVW, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AMOVD, C_REG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AMOVB, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM, 0}, - {AMOVBU, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM, 0}, - {AMOVH, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM, 0}, - {AMOVW, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM, 0}, - {AMOVD, C_ADDR, C_NONE, C_REG, 65, 8, 0, LFROM, 0}, + {AMOVD, C_VCONADDR, C_NONE, C_REG, 68, 8, 0, 0, 0}, + {AMOVB, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AMOVBU, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AMOVH, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AMOVW, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AMOVD, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AMOVB, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0}, + {AMOVBU, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0}, + {AMOVH, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0}, + {AMOVW, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0}, + {AMOVD, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0}, {AMUL, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0}, {AMUL, C_REG, C_NONE, C_REG, 15, 4, 0, 0, 0}, {AMADD, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0}, @@ -447,10 +449,10 @@ var optab = []Optab{ {AFMOVS, C_LOREG, C_NONE, C_FREG, 31, 8, 0, LFROM, 0}, {AFMOVD, C_LAUTO, C_NONE, C_FREG, 31, 8, REGSP, LFROM, 0}, {AFMOVD, C_LOREG, C_NONE, C_FREG, 31, 8, 0, LFROM, 0}, - {AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 8, 0, LFROM, 0}, - {AFMOVD, C_FREG, C_NONE, C_ADDR, 64, 8, 0, LTO, 0}, - {AFMOVD, C_ADDR, C_NONE, C_FREG, 65, 8, 0, LFROM, 0}, + {AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 12, 0, 0, 0}, + {AFMOVD, C_FREG, C_NONE, C_ADDR, 64, 12, 0, 0, 0}, + {AFMOVD, C_ADDR, C_NONE, C_FREG, 65, 12, 0, 0, 0}, {AFADDS, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0}, {AFADDS, C_FREG, C_FREG, C_FREG, 54, 4, 0, 0, 0}, {AFADDS, C_FCON, C_NONE, C_FREG, 54, 4, 0, 0, 0}, @@ -1176,12 +1178,7 @@ func cmp(a int, b int) bool { } case C_VCON: - if b == C_VCONADDR { - return true - } else { - return cmp(C_LCON, b) - } - fallthrough + return cmp(C_LCON, b) case C_LACON: if b == C_AACON { @@ -2724,21 +2721,27 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) { } /* reloc ops */ - case 64: /* movT R,addr */ - o1 = omovlit(ctxt, AMOVD, p, &p.To, REGTMP) - - if !(o1 != 0) { - break - } - o2 = olsr12u(ctxt, int32(opstr12(ctxt, int(p.As))), 0, REGTMP, int(p.From.Reg)) - - case 65: /* movT addr,R */ - o1 = omovlit(ctxt, AMOVD, p, &p.From, REGTMP) + case 64: /* movT R,addr -> adrp + add + movT R, (REGTMP) */ + o1 = ADR(1, 0, REGTMP) + o2 = opirr(ctxt, AADD) | REGTMP&31<<5 | REGTMP&31 + rel := obj.Addrel(ctxt.Cursym) + rel.Off = int32(ctxt.Pc) + rel.Siz = 8 + rel.Sym = p.To.Sym + rel.Add = p.To.Offset + rel.Type = obj.R_ADDRARM64 + o3 = olsr12u(ctxt, int32(opstr12(ctxt, int(p.As))), 0, REGTMP, int(p.From.Reg)) - if !(o1 != 0) { - break - } - o2 = olsr12u(ctxt, int32(opldr12(ctxt, int(p.As))), 0, REGTMP, int(p.To.Reg)) + case 65: /* movT addr,R -> adrp + add + movT (REGTMP), R */ + o1 = ADR(1, 0, REGTMP) + o2 = opirr(ctxt, AADD) | REGTMP&31<<5 | REGTMP&31 + rel := obj.Addrel(ctxt.Cursym) + rel.Off = int32(ctxt.Pc) + rel.Siz = 8 + rel.Sym = p.From.Sym + rel.Add = p.From.Offset + rel.Type = obj.R_ADDRARM64 + o3 = olsr12u(ctxt, int32(opldr12(ctxt, int(p.As))), 0, REGTMP, int(p.To.Reg)) case 66: /* ldp O(R)!, (r1, r2); ldp (R)O!, (r1, r2) */ v := int32(p.From.Offset) @@ -2767,6 +2770,19 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) { } o1 |= uint32(int64(2<<30|5<<27|((uint32(v)/8)&0x7f)<<15) | p.From.Offset<<10 | int64(uint32(p.To.Reg&31)<<5) | int64(p.From.Reg&31)) + case 68: /* movT $vconaddr(SB), reg -> adrp + add + reloc */ + if p.As == AMOVW { + ctxt.Diag("invalid load of 32-bit address: %v", p) + } + o1 = ADR(1, 0, uint32(p.To.Reg)) + o2 = opirr(ctxt, AADD) | uint32(p.To.Reg&31)<<5 | uint32(p.To.Reg&31) + rel := obj.Addrel(ctxt.Cursym) + rel.Off = int32(ctxt.Pc) + rel.Siz = 8 + rel.Sym = p.From.Sym + rel.Add = p.From.Offset + rel.Type = obj.R_ADDRARM64 + // This is supposed to be something that stops execution. // It's not supposed to be reached, ever, but if it is, we'd // like to be able to tell how we got there. Assemble as diff --git a/src/cmd/internal/obj/link.go b/src/cmd/internal/obj/link.go index 2a1df516c3..a714057028 100644 --- a/src/cmd/internal/obj/link.go +++ b/src/cmd/internal/obj/link.go @@ -362,6 +362,7 @@ type Reloc struct { const ( R_ADDR = 1 + iota R_ADDRPOWER + R_ADDRARM64 R_SIZE R_CALL R_CALLARM