From: Cherry Zhang Date: Fri, 22 Jul 2016 10:41:14 +0000 (-0400) Subject: [dev.ssa] cmd/compile: add more on ARM64 SSA X-Git-Tag: go1.8beta1~1892^2^2~20 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=83208504fe2bbe91dae99111593de54cca1cdca0;p=gostls13.git [dev.ssa] cmd/compile: add more on ARM64 SSA Support the following: - Shifts. ARM64 machine instructions only use lowest 6 bits of the shift (i.e. mod 64). Use conditional selection instruction to ensure Go semantics. - Zero/Move. Alignment is ensured. - Hmul, Avg64u, Sqrt. - reserve R18 (platform register in ARM64 ABI) and R29 (frame pointer in ARM64 ABI). Everything compiles, all.bash passed (with non-SSA test disabled). Change-Id: Ia8ed58dae5cbc001946f0b889357b258655078b1 Reviewed-on: https://go-review.googlesource.com/25290 Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot Reviewed-by: David Chase --- diff --git a/src/cmd/compile/internal/arm64/prog.go b/src/cmd/compile/internal/arm64/prog.go index d504d0f0ee..4192db04b1 100644 --- a/src/cmd/compile/internal/arm64/prog.go +++ b/src/cmd/compile/internal/arm64/prog.go @@ -44,24 +44,35 @@ var progtable = [arm64.ALAST & obj.AMask]obj.ProgInfo{ // Integer arm64.AADD & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.ASUB & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, - arm64.ANEG & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.ANEG & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RightWrite}, arm64.AAND & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.AORR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.AEOR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AMVN & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RightWrite}, arm64.AMUL & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AMULW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.ASMULL & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.AUMULL & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, - arm64.ASMULH & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, - arm64.AUMULH & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.ASMULH & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AUMULH & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.ASDIV & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.AUDIV & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.ASDIVW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AUDIVW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AREM & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AUREM & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AREMW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, + arm64.AUREMW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.ALSL & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.ALSR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.AASR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.ACMP & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead}, + arm64.ACMPW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead}, arm64.AADC & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite | gc.UseCarry}, arm64.AROR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, arm64.AADDS & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite | gc.SetCarry}, + arm64.ACSET & obj.AMask: {Flags: gc.SizeQ | gc.RightWrite}, + arm64.ACSEL & obj.AMask: {Flags: gc.SizeQ | gc.RegRead | gc.RightWrite}, // Floating point. arm64.AFADDD & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite}, diff --git a/src/cmd/compile/internal/arm64/ssa.go b/src/cmd/compile/internal/arm64/ssa.go index 90dab7f4dc..52580242dc 100644 --- a/src/cmd/compile/internal/arm64/ssa.go +++ b/src/cmd/compile/internal/arm64/ssa.go @@ -32,7 +32,7 @@ var ssaRegToReg = []int16{ arm64.REG_R15, arm64.REG_R16, arm64.REG_R17, - arm64.REG_R18, + arm64.REG_R18, // platform register, not used arm64.REG_R19, arm64.REG_R20, arm64.REG_R21, @@ -42,8 +42,8 @@ var ssaRegToReg = []int16{ arm64.REG_R25, arm64.REG_R26, // R27 = REGTMP not used in regalloc - arm64.REGG, // R28 - arm64.REG_R29, + arm64.REGG, // R28 + arm64.REG_R29, // frame pointer, not used // R30 = REGLINK not used in regalloc arm64.REGSP, // R31 @@ -229,6 +229,11 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { ssa.OpARM64XOR, ssa.OpARM64BIC, ssa.OpARM64MUL, + ssa.OpARM64MULW, + ssa.OpARM64MULH, + ssa.OpARM64UMULH, + ssa.OpARM64MULL, + ssa.OpARM64UMULL, ssa.OpARM64DIV, ssa.OpARM64UDIV, ssa.OpARM64DIVW, @@ -237,6 +242,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { ssa.OpARM64UMOD, ssa.OpARM64MODW, ssa.OpARM64UMODW, + ssa.OpARM64SLL, + ssa.OpARM64SRL, + ssa.OpARM64SRA, ssa.OpARM64FADDS, ssa.OpARM64FADDD, ssa.OpARM64FSUBS, @@ -259,7 +267,12 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { ssa.OpARM64ANDconst, ssa.OpARM64ORconst, ssa.OpARM64XORconst, - ssa.OpARM64BICconst: + ssa.OpARM64BICconst, + ssa.OpARM64SLLconst, + ssa.OpARM64SRLconst, + ssa.OpARM64SRAconst, + ssa.OpARM64RORconst, + ssa.OpARM64RORWconst: p := gc.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_CONST p.From.Offset = v.AuxInt @@ -415,6 +428,107 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { p.From.Reg = gc.SSARegNum(v.Args[0]) p.To.Type = obj.TYPE_REG p.To.Reg = gc.SSARegNum(v) + case ssa.OpARM64CSELULT: + p := gc.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg + p.From.Reg = arm64.COND_LO + p.Reg = gc.SSARegNum(v.Args[0]) + p.From3 = &obj.Addr{Type: obj.TYPE_REG, Reg: gc.SSARegNum(v.Args[1])} + p.To.Type = obj.TYPE_REG + p.To.Reg = gc.SSARegNum(v) + case ssa.OpARM64DUFFZERO: + // runtime.duffzero expects start address - 8 in R16 + p := gc.Prog(arm64.ASUB) + p.From.Type = obj.TYPE_CONST + p.From.Offset = 8 + p.Reg = gc.SSARegNum(v.Args[0]) + p.To.Type = obj.TYPE_REG + p.To.Reg = arm64.REG_R16 + p = gc.Prog(obj.ADUFFZERO) + p.To.Type = obj.TYPE_MEM + p.To.Name = obj.NAME_EXTERN + p.To.Sym = gc.Linksym(gc.Pkglookup("duffzero", gc.Runtimepkg)) + p.To.Offset = v.AuxInt + case ssa.OpARM64LoweredZero: + // MOVD.P ZR, 8(R16) + // CMP Rarg1, R16 + // BLE -2(PC) + // arg1 is the address of the last element to zero + // auxint is alignment + var sz int64 + var mov obj.As + switch { + case v.AuxInt%8 == 0: + sz = 8 + mov = arm64.AMOVD + case v.AuxInt%4 == 0: + sz = 4 + mov = arm64.AMOVW + case v.AuxInt%2 == 0: + sz = 2 + mov = arm64.AMOVH + default: + sz = 1 + mov = arm64.AMOVB + } + p := gc.Prog(mov) + p.Scond = arm64.C_XPOST + p.From.Type = obj.TYPE_REG + p.From.Reg = arm64.REGZERO + p.To.Type = obj.TYPE_MEM + p.To.Reg = arm64.REG_R16 + p.To.Offset = sz + p2 := gc.Prog(arm64.ACMP) + p2.From.Type = obj.TYPE_REG + p2.From.Reg = gc.SSARegNum(v.Args[1]) + p2.Reg = arm64.REG_R16 + p3 := gc.Prog(arm64.ABLE) + p3.To.Type = obj.TYPE_BRANCH + gc.Patch(p3, p) + case ssa.OpARM64LoweredMove: + // MOVD.P 8(R16), Rtmp + // MOVD.P Rtmp, 8(R17) + // CMP Rarg2, R16 + // BLE -3(PC) + // arg2 is the address of the last element of src + // auxint is alignment + var sz int64 + var mov obj.As + switch { + case v.AuxInt%8 == 0: + sz = 8 + mov = arm64.AMOVD + case v.AuxInt%4 == 0: + sz = 4 + mov = arm64.AMOVW + case v.AuxInt%2 == 0: + sz = 2 + mov = arm64.AMOVH + default: + sz = 1 + mov = arm64.AMOVB + } + p := gc.Prog(mov) + p.Scond = arm64.C_XPOST + p.From.Type = obj.TYPE_MEM + p.From.Reg = arm64.REG_R16 + p.From.Offset = sz + p.To.Type = obj.TYPE_REG + p.To.Reg = arm64.REGTMP + p2 := gc.Prog(mov) + p2.Scond = arm64.C_XPOST + p2.From.Type = obj.TYPE_REG + p2.From.Reg = arm64.REGTMP + p2.To.Type = obj.TYPE_MEM + p2.To.Reg = arm64.REG_R17 + p2.To.Offset = sz + p3 := gc.Prog(arm64.ACMP) + p3.From.Type = obj.TYPE_REG + p3.From.Reg = gc.SSARegNum(v.Args[2]) + p3.Reg = arm64.REG_R16 + p4 := gc.Prog(arm64.ABLE) + p4.To.Type = obj.TYPE_BRANCH + gc.Patch(p4, p) case ssa.OpARM64CALLstatic: if v.Aux.(*gc.Sym) == gc.Deferreturn.Sym { // Deferred calls will appear to be returning to @@ -507,7 +621,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { ssa.OpARM64GreaterEqualU: // generate boolean values using CSET p := gc.Prog(arm64.ACSET) - p.From.Type = obj.TYPE_REG + p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg p.From.Reg = condBits[v.Op] p.To.Type = obj.TYPE_REG p.To.Reg = gc.SSARegNum(v) diff --git a/src/cmd/compile/internal/ssa/gen/ARM64.rules b/src/cmd/compile/internal/ssa/gen/ARM64.rules index 9290b3c186..9b80094f86 100644 --- a/src/cmd/compile/internal/ssa/gen/ARM64.rules +++ b/src/cmd/compile/internal/ssa/gen/ARM64.rules @@ -19,12 +19,21 @@ (Sub64F x y) -> (FSUBD x y) (Mul64 x y) -> (MUL x y) -(Mul32 x y) -> (MUL x y) -(Mul16 x y) -> (MUL x y) -(Mul8 x y) -> (MUL x y) +(Mul32 x y) -> (MULW x y) +(Mul16 x y) -> (MULW x y) +(Mul8 x y) -> (MULW x y) (Mul32F x y) -> (FMULS x y) (Mul64F x y) -> (FMULD x y) +(Hmul64 x y) -> (MULH x y) +(Hmul64u x y) -> (UMULH x y) +(Hmul32 x y) -> (SRAconst (MULL x y) [32]) +(Hmul32u x y) -> (SRAconst (UMULL x y) [32]) +(Hmul16 x y) -> (SRAconst (MULW (SignExt16to32 x) (SignExt16to32 y)) [16]) +(Hmul16u x y) -> (SRLconst (MUL (ZeroExt16to32 x) (ZeroExt16to32 y)) [16]) +(Hmul8 x y) -> (SRAconst (MULW (SignExt8to32 x) (SignExt8to32 y)) [8]) +(Hmul8u x y) -> (SRLconst (MUL (ZeroExt8to32 x) (ZeroExt8to32 y)) [8]) + (Div64 x y) -> (DIV x y) (Div64u x y) -> (UDIV x y) (Div32 x y) -> (DIVW x y) @@ -45,6 +54,8 @@ (Mod8 x y) -> (MODW (SignExt8to32 x) (SignExt8to32 y)) (Mod8u x y) -> (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) +(Avg64u x y) -> (ADD (ADD (SRLconst x [1]) (SRLconst y [1])) (AND (AND x y) (MOVDconst [1]))) + (And64 x y) -> (AND x y) (And32 x y) -> (AND x y) (And16 x y) -> (AND x y) @@ -73,12 +84,112 @@ (Com16 x) -> (MVN x) (Com8 x) -> (MVN x) +(Sqrt x) -> (FSQRTD x) + // boolean ops -- booleans are represented with 0=false, 1=true (AndB x y) -> (AND x y) (OrB x y) -> (OR x y) -(EqB x y) -> (XORconst [1] (XOR x y)) +(EqB x y) -> (XOR (MOVDconst [1]) (XOR x y)) (NeqB x y) -> (XOR x y) -(Not x) -> (XORconst [1] x) +(Not x) -> (XOR (MOVDconst [1]) x) + +// constant shifts +(Lsh64x64 x (MOVDconst [c])) && uint64(c) < 64 -> (SLLconst x [c]) +(Rsh64x64 x (MOVDconst [c])) && uint64(c) < 64 -> (SRAconst x [c]) +(Rsh64Ux64 x (MOVDconst [c])) && uint64(c) < 64 -> (SRLconst x [c]) +(Lsh32x64 x (MOVDconst [c])) && uint64(c) < 32 -> (SLLconst x [c]) +(Rsh32x64 x (MOVDconst [c])) && uint64(c) < 32 -> (SRAconst (SignExt32to64 x) [c]) +(Rsh32Ux64 x (MOVDconst [c])) && uint64(c) < 32 -> (SRLconst (ZeroExt32to64 x) [c]) +(Lsh16x64 x (MOVDconst [c])) && uint64(c) < 16 -> (SLLconst x [c]) +(Rsh16x64 x (MOVDconst [c])) && uint64(c) < 16 -> (SRAconst (SignExt16to64 x) [c]) +(Rsh16Ux64 x (MOVDconst [c])) && uint64(c) < 16 -> (SRLconst (ZeroExt16to64 x) [c]) +(Lsh8x64 x (MOVDconst [c])) && uint64(c) < 8 -> (SLLconst x [c]) +(Rsh8x64 x (MOVDconst [c])) && uint64(c) < 8 -> (SRAconst (SignExt8to64 x) [c]) +(Rsh8Ux64 x (MOVDconst [c])) && uint64(c) < 8 -> (SRLconst (ZeroExt8to64 x) [c]) + +// large constant shifts +(Lsh64x64 _ (MOVDconst [c])) && uint64(c) >= 64 -> (MOVDconst [0]) +(Rsh64Ux64 _ (MOVDconst [c])) && uint64(c) >= 64 -> (MOVDconst [0]) +(Lsh32x64 _ (MOVDconst [c])) && uint64(c) >= 32 -> (MOVDconst [0]) +(Rsh32Ux64 _ (MOVDconst [c])) && uint64(c) >= 32 -> (MOVDconst [0]) +(Lsh16x64 _ (MOVDconst [c])) && uint64(c) >= 16 -> (MOVDconst [0]) +(Rsh16Ux64 _ (MOVDconst [c])) && uint64(c) >= 16 -> (MOVDconst [0]) +(Lsh8x64 _ (MOVDconst [c])) && uint64(c) >= 8 -> (MOVDconst [0]) +(Rsh8Ux64 _ (MOVDconst [c])) && uint64(c) >= 8 -> (MOVDconst [0]) + +// large constant signed right shift, we leave the sign bit +(Rsh64x64 x (MOVDconst [c])) && uint64(c) >= 64 -> (SRAconst x [63]) +(Rsh32x64 x (MOVDconst [c])) && uint64(c) >= 32 -> (SRAconst (SignExt32to64 x) [63]) +(Rsh16x64 x (MOVDconst [c])) && uint64(c) >= 16 -> (SRAconst (SignExt16to64 x) [63]) +(Rsh8x64 x (MOVDconst [c])) && uint64(c) >= 8 -> (SRAconst (SignExt8to64 x) [63]) + +// shifts +// hardware instruction uses only the low 6 bits of the shift +// we compare to 64 to ensure Go semantics for large shifts +(Lsh64x64 x y) -> (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) +(Lsh64x32 x y) -> (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Lsh64x16 x y) -> (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Lsh64x8 x y) -> (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Lsh32x64 x y) -> (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) +(Lsh32x32 x y) -> (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Lsh32x16 x y) -> (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Lsh32x8 x y) -> (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Lsh16x64 x y) -> (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) +(Lsh16x32 x y) -> (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Lsh16x16 x y) -> (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Lsh16x8 x y) -> (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Lsh8x64 x y) -> (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) +(Lsh8x32 x y) -> (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Lsh8x16 x y) -> (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Lsh8x8 x y) -> (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Rsh64Ux64 x y) -> (CSELULT (SRL x y) (Const64 [0]) (CMPconst [64] y)) +(Rsh64Ux32 x y) -> (CSELULT (SRL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Rsh64Ux16 x y) -> (CSELULT (SRL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Rsh64Ux8 x y) -> (CSELULT (SRL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Rsh32Ux64 x y) -> (CSELULT (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) +(Rsh32Ux32 x y) -> (CSELULT (SRL (ZeroExt32to64 x) (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Rsh32Ux16 x y) -> (CSELULT (SRL (ZeroExt32to64 x) (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Rsh32Ux8 x y) -> (CSELULT (SRL (ZeroExt32to64 x) (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Rsh16Ux64 x y) -> (CSELULT (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) +(Rsh16Ux32 x y) -> (CSELULT (SRL (ZeroExt16to64 x) (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Rsh16Ux16 x y) -> (CSELULT (SRL (ZeroExt16to64 x) (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Rsh16Ux8 x y) -> (CSELULT (SRL (ZeroExt16to64 x) (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Rsh8Ux64 x y) -> (CSELULT (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) +(Rsh8Ux32 x y) -> (CSELULT (SRL (ZeroExt8to64 x) (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) +(Rsh8Ux16 x y) -> (CSELULT (SRL (ZeroExt8to64 x) (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) +(Rsh8Ux8 x y) -> (CSELULT (SRL (ZeroExt8to64 x) (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + +(Rsh64x64 x y) -> (SRA x (CSELULT y (Const64 [63]) (CMPconst [64] y))) +(Rsh64x32 x y) -> (SRA x (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) +(Rsh64x16 x y) -> (SRA x (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) +(Rsh64x8 x y) -> (SRA x (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) + +(Rsh32x64 x y) -> (SRA (SignExt32to64 x) (CSELULT y (Const64 [63]) (CMPconst [64] y))) +(Rsh32x32 x y) -> (SRA (SignExt32to64 x) (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) +(Rsh32x16 x y) -> (SRA (SignExt32to64 x) (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) +(Rsh32x8 x y) -> (SRA (SignExt32to64 x) (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) + +(Rsh16x64 x y) -> (SRA (SignExt16to64 x) (CSELULT y (Const64 [63]) (CMPconst [64] y))) +(Rsh16x32 x y) -> (SRA (SignExt16to64 x) (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) +(Rsh16x16 x y) -> (SRA (SignExt16to64 x) (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) +(Rsh16x8 x y) -> (SRA (SignExt16to64 x) (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) + +(Rsh8x64 x y) -> (SRA (SignExt8to64 x) (CSELULT y (Const64 [63]) (CMPconst [64] y))) +(Rsh8x32 x y) -> (SRA (SignExt8to64 x) (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) +(Rsh8x16 x y) -> (SRA (SignExt8to64 x) (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) +(Rsh8x8 x y) -> (SRA (SignExt8to64 x) (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) + +(Lrot64 x [c]) -> (RORconst x [64-c&63]) +(Lrot32 x [c]) -> (RORWconst x [32-c&31]) +(Lrot16 x [c]) -> (OR (SLLconst x [c&15]) (SRLconst (ZeroExt16to64 x) [16-c&15])) +(Lrot8 x [c]) -> (OR (SLLconst x [c&7]) (SRLconst (ZeroExt8to64 x) [8-c&7])) // constants (Const64 [val]) -> (MOVDconst [val]) @@ -224,6 +335,129 @@ (Store [4] ptr val mem) && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem) (Store [8] ptr val mem) && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem) +// zeroing +(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVDconst [0]) mem) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore ptr (MOVDconst [0]) mem) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 -> + (MOVBstore [1] ptr (MOVDconst [0]) + (MOVBstore ptr (MOVDconst [0]) mem)) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 -> + (MOVWstore ptr (MOVDconst [0]) mem) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore [2] ptr (MOVDconst [0]) + (MOVHstore ptr (MOVDconst [0]) mem)) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 -> + (MOVBstore [3] ptr (MOVDconst [0]) + (MOVBstore [2] ptr (MOVDconst [0]) + (MOVBstore [1] ptr (MOVDconst [0]) + (MOVBstore ptr (MOVDconst [0]) mem)))) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 -> + (MOVDstore ptr (MOVDconst [0]) mem) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 -> + (MOVWstore [4] ptr (MOVDconst [0]) + (MOVWstore ptr (MOVDconst [0]) mem)) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore [6] ptr (MOVDconst [0]) + (MOVHstore [4] ptr (MOVDconst [0]) + (MOVHstore [2] ptr (MOVDconst [0]) + (MOVHstore ptr (MOVDconst [0]) mem)))) + +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 -> + (MOVBstore [2] ptr (MOVDconst [0]) + (MOVBstore [1] ptr (MOVDconst [0]) + (MOVBstore ptr (MOVDconst [0]) mem))) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore [4] ptr (MOVDconst [0]) + (MOVHstore [2] ptr (MOVDconst [0]) + (MOVHstore ptr (MOVDconst [0]) mem))) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 -> + (MOVWstore [8] ptr (MOVDconst [0]) + (MOVWstore [4] ptr (MOVDconst [0]) + (MOVWstore ptr (MOVDconst [0]) mem))) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 -> + (MOVDstore [8] ptr (MOVDconst [0]) + (MOVDstore ptr (MOVDconst [0]) mem)) +(Zero [s] ptr mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 -> + (MOVDstore [16] ptr (MOVDconst [0]) + (MOVDstore [8] ptr (MOVDconst [0]) + (MOVDstore ptr (MOVDconst [0]) mem))) + +// medium zeroing uses a duff device +// 4, 8, and 128 are magic constants, see runtime/mkduff.go +(Zero [s] ptr mem) + && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 + && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice -> + (DUFFZERO [4 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem) + +// large or unaligned zeroing uses a loop +(Zero [s] ptr mem) + && (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0 -> + (LoweredZero [SizeAndAlign(s).Align()] + ptr + (ADDconst [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)] ptr) + mem) + +// moves +(Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBUload src mem) mem) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore dst (MOVHUload src mem) mem) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> + (MOVBstore [1] dst (MOVBUload [1] src mem) + (MOVBstore dst (MOVBUload src mem) mem)) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 -> + (MOVWstore dst (MOVWUload src mem) mem) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore [2] dst (MOVHUload [2] src mem) + (MOVHstore dst (MOVHUload src mem) mem)) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> + (MOVBstore [3] dst (MOVBUload [3] src mem) + (MOVBstore [2] dst (MOVBUload [2] src mem) + (MOVBstore [1] dst (MOVBUload [1] src mem) + (MOVBstore dst (MOVBUload src mem) mem)))) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 -> + (MOVDstore dst (MOVDload src mem) mem) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 -> + (MOVWstore [4] dst (MOVWUload [4] src mem) + (MOVWstore dst (MOVWUload src mem) mem)) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore [6] dst (MOVHUload [6] src mem) + (MOVHstore [4] dst (MOVHUload [4] src mem) + (MOVHstore [2] dst (MOVHUload [2] src mem) + (MOVHstore dst (MOVHUload src mem) mem)))) + +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 -> + (MOVBstore [2] dst (MOVBUload [2] src mem) + (MOVBstore [1] dst (MOVBUload [1] src mem) + (MOVBstore dst (MOVBUload src mem) mem))) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 -> + (MOVHstore [4] dst (MOVHUload [4] src mem) + (MOVHstore [2] dst (MOVHUload [2] src mem) + (MOVHstore dst (MOVHUload src mem) mem))) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 -> + (MOVWstore [8] dst (MOVWUload [8] src mem) + (MOVWstore [4] dst (MOVWUload [4] src mem) + (MOVWstore dst (MOVWUload src mem) mem))) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 -> + (MOVDstore [8] dst (MOVDload [8] src mem) + (MOVDstore dst (MOVDload src mem) mem)) +(Move [s] dst src mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 -> + (MOVDstore [16] dst (MOVDload [16] src mem) + (MOVDstore [8] dst (MOVDload [8] src mem) + (MOVDstore dst (MOVDload src mem) mem))) + +// large or unaligned move uses a loop +// DUFFCOPY is not implemented on ARM64 (TODO) +(Move [s] dst src mem) + && SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0 -> + (LoweredMove [SizeAndAlign(s).Align()] + dst + src + (ADDconst src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) + mem) + // calls (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) diff --git a/src/cmd/compile/internal/ssa/gen/ARM64Ops.go b/src/cmd/compile/internal/ssa/gen/ARM64Ops.go index 9925a65b00..e6ffe13663 100644 --- a/src/cmd/compile/internal/ssa/gen/ARM64Ops.go +++ b/src/cmd/compile/internal/ssa/gen/ARM64Ops.go @@ -48,7 +48,7 @@ var regNamesARM64 = []string{ "R15", "R16", "R17", - "R18", // platform register? + "R18", // platform register, not used "R19", "R20", "R21", @@ -59,7 +59,7 @@ var regNamesARM64 = []string{ "R26", // R27 = REGTMP not used in regalloc "g", // aka R28 - "R29", // frame pointer? + "R29", // frame pointer, not used // R30 = REGLINK not used in regalloc "SP", // aka R31 @@ -124,7 +124,7 @@ func init() { // Common individual register masks var ( - gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29") + gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26") gpg = gp | buildReg("g") gpsp = gp | buildReg("SP") gpspg = gpg | buildReg("SP") @@ -142,8 +142,8 @@ func init() { //gp1flags1 = regInfo{inputs: []regMask{gp, flags}, outputs: []regMask{gp}} gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}} //gp21cf = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}, clobbers: flags} // cf: clobbers flags - gp2flags = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{flags}} - //gp2flags1 = regInfo{inputs: []regMask{gp, gp, flags}, outputs: []regMask{gp}} + gp2flags = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{flags}} + gp2flags1 = regInfo{inputs: []regMask{gp, gp, flags}, outputs: []regMask{gp}} //gp22 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp, gp}} //gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}} //gp3flags = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{flags}} @@ -165,19 +165,24 @@ func init() { ) ops := []opData{ // binary ops - {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 - {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int32"}, // arg0 + auxInt - {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1 - {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int32"}, // arg0 - auxInt - {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1 - {name: "DIV", argLength: 2, reg: gp21, asm: "SDIV"}, // arg0 / arg1, signed - {name: "UDIV", argLength: 2, reg: gp21, asm: "UDIV"}, // arg0 / arg1, unsighed - {name: "DIVW", argLength: 2, reg: gp21, asm: "SDIVW"}, // arg0 / arg1, signed, 32 bit - {name: "UDIVW", argLength: 2, reg: gp21, asm: "UDIVW"}, // arg0 / arg1, unsighed, 32 bit - {name: "MOD", argLength: 2, reg: gp21, asm: "REM"}, // arg0 % arg1, signed - {name: "UMOD", argLength: 2, reg: gp21, asm: "UREM"}, // arg0 % arg1, unsigned - {name: "MODW", argLength: 2, reg: gp21, asm: "REMW"}, // arg0 % arg1, signed, 32 bit - {name: "UMODW", argLength: 2, reg: gp21, asm: "UREMW"}, // arg0 % arg1, unsigned, 32 bit + {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1 + {name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int64"}, // arg0 + auxInt + {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1 + {name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int64"}, // arg0 - auxInt + {name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true}, // arg0 * arg1 + {name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true}, // arg0 * arg1, 32-bit + {name: "MULH", argLength: 2, reg: gp21, asm: "SMULH", commutative: true}, // (arg0 * arg1) >> 64, signed + {name: "UMULH", argLength: 2, reg: gp21, asm: "UMULH", commutative: true}, // (arg0 * arg1) >> 64, unsigned + {name: "MULL", argLength: 2, reg: gp21, asm: "SMULL", commutative: true}, // arg0 * arg1, signed, 32-bit mult results in 64-bit + {name: "UMULL", argLength: 2, reg: gp21, asm: "UMULL", commutative: true}, // arg0 * arg1, unsigned, 32-bit mult results in 64-bit + {name: "DIV", argLength: 2, reg: gp21, asm: "SDIV"}, // arg0 / arg1, signed + {name: "UDIV", argLength: 2, reg: gp21, asm: "UDIV"}, // arg0 / arg1, unsighed + {name: "DIVW", argLength: 2, reg: gp21, asm: "SDIVW"}, // arg0 / arg1, signed, 32 bit + {name: "UDIVW", argLength: 2, reg: gp21, asm: "UDIVW"}, // arg0 / arg1, unsighed, 32 bit + {name: "MOD", argLength: 2, reg: gp21, asm: "REM"}, // arg0 % arg1, signed + {name: "UMOD", argLength: 2, reg: gp21, asm: "UREM"}, // arg0 % arg1, unsigned + {name: "MODW", argLength: 2, reg: gp21, asm: "REMW"}, // arg0 % arg1, signed, 32 bit + {name: "UMODW", argLength: 2, reg: gp21, asm: "UREMW"}, // arg0 % arg1, unsigned, 32 bit {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true}, // arg0 + arg1 {name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true}, // arg0 + arg1 @@ -189,13 +194,13 @@ func init() { {name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD"}, // arg0 / arg1 {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1 - {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32"}, // arg0 & auxInt + {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"}, // arg0 & auxInt {name: "OR", argLength: 2, reg: gp21, asm: "ORR", commutative: true}, // arg0 | arg1 - {name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int32"}, // arg0 | auxInt + {name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int64"}, // arg0 | auxInt {name: "XOR", argLength: 2, reg: gp21, asm: "EOR", commutative: true}, // arg0 ^ arg1 - {name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int32"}, // arg0 ^ auxInt + {name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int64"}, // arg0 ^ auxInt {name: "BIC", argLength: 2, reg: gp21, asm: "BIC"}, // arg0 &^ arg1 - {name: "BICconst", argLength: 1, reg: gp11, asm: "BIC", aux: "Int32"}, // arg0 &^ auxInt + {name: "BICconst", argLength: 1, reg: gp11, asm: "BIC", aux: "Int64"}, // arg0 &^ auxInt // unary ops {name: "MVN", argLength: 1, reg: gp11, asm: "MVN"}, // ^arg0 @@ -204,20 +209,30 @@ func init() { {name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD"}, // -arg0, float64 {name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD"}, // sqrt(arg0), float64 + // shifts + {name: "SLL", argLength: 2, reg: gp21, asm: "LSL"}, // arg0 << arg1, shift amount is mod 64 + {name: "SLLconst", argLength: 1, reg: gp11, asm: "LSL", aux: "Int64"}, // arg0 << auxInt + {name: "SRL", argLength: 2, reg: gp21, asm: "LSR"}, // arg0 >> arg1, unsigned, shift amount is mod 64 + {name: "SRLconst", argLength: 1, reg: gp11, asm: "LSR", aux: "Int64"}, // arg0 >> auxInt, unsigned + {name: "SRA", argLength: 2, reg: gp21, asm: "ASR"}, // arg0 >> arg1, signed, shift amount is mod 64 + {name: "SRAconst", argLength: 1, reg: gp11, asm: "ASR", aux: "Int64"}, // arg0 >> auxInt, signed + {name: "RORconst", argLength: 1, reg: gp11, asm: "ROR", aux: "Int64"}, // arg0 right rotate by auxInt bits + {name: "RORWconst", argLength: 1, reg: gp11, asm: "RORW", aux: "Int64"}, // uint32(arg0) right rotate by auxInt bits + // comparisons {name: "CMP", argLength: 2, reg: gp2flags, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1 - {name: "CMPconst", argLength: 1, reg: gp1flags, asm: "CMP", aux: "Int32", typ: "Flags"}, // arg0 compare to auxInt + {name: "CMPconst", argLength: 1, reg: gp1flags, asm: "CMP", aux: "Int64", typ: "Flags"}, // arg0 compare to auxInt {name: "CMPW", argLength: 2, reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1, 32 bit {name: "CMPWconst", argLength: 1, reg: gp1flags, asm: "CMPW", aux: "Int32", typ: "Flags"}, // arg0 compare to auxInt, 32 bit {name: "CMN", argLength: 2, reg: gp2flags, asm: "CMN", typ: "Flags"}, // arg0 compare to -arg1 - {name: "CMNconst", argLength: 1, reg: gp1flags, asm: "CMN", aux: "Int32", typ: "Flags"}, // arg0 compare to -auxInt + {name: "CMNconst", argLength: 1, reg: gp1flags, asm: "CMN", aux: "Int64", typ: "Flags"}, // arg0 compare to -auxInt {name: "CMNW", argLength: 2, reg: gp2flags, asm: "CMNW", typ: "Flags"}, // arg0 compare to -arg1, 32 bit {name: "CMNWconst", argLength: 1, reg: gp1flags, asm: "CMNW", aux: "Int32", typ: "Flags"}, // arg0 compare to -auxInt, 32 bit {name: "FCMPS", argLength: 2, reg: fp2flags, asm: "FCMPS", typ: "Flags"}, // arg0 compare to arg1, float32 {name: "FCMPD", argLength: 2, reg: fp2flags, asm: "FCMPD", typ: "Flags"}, // arg0 compare to arg1, float64 // moves - {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVD", typ: "UInt32", rematerializeable: true}, // 32 low bits of auxint + {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "UInt64", rematerializeable: true}, // 32 low bits of auxint {name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVS", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float {name: "FMOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float @@ -268,6 +283,9 @@ func init() { {name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD"}, // float32 -> float64 {name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS"}, // float64 -> float32 + // conditional instructions + {name: "CSELULT", argLength: 3, reg: gp2flags1, asm: "CSEL"}, // returns arg0 if flags indicates unsigned LT, arg1 otherwise, arg2=flags + // function calls {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R26"), 0}, clobbers: callerSave}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem @@ -289,6 +307,66 @@ func init() { {name: "GreaterThanU", argLength: 1, reg: readflags}, // bool, true flags encode unsigned x>y false otherwise. {name: "GreaterEqualU", argLength: 1, reg: readflags}, // bool, true flags encode unsigned x>=y false otherwise. + // duffzero + // arg0 = address of memory to zero + // arg1 = mem + // auxint = offset into duffzero code to start executing + // returns mem + // R16 aka arm64.REGRT1 changed as side effect + { + name: "DUFFZERO", + aux: "Int64", + argLength: 2, + reg: regInfo{ + inputs: []regMask{gp}, + clobbers: buildReg("R16"), + }, + }, + + // large zeroing + // arg0 = address of memory to zero (in R16 aka arm64.REGRT1, changed as side effect) + // arg1 = address of the last element to zero + // arg2 = mem + // auxint = alignment + // returns mem + // MOVD.P ZR, 8(R16) + // CMP Rarg1, R16 + // BLE -2(PC) + // Note: the-end-of-the-memory may be not a valid pointer. it's a problem if it is spilled. + // the-end-of-the-memory - 8 is with the area to zero, ok to spill. + { + name: "LoweredZero", + aux: "Int64", + argLength: 3, + reg: regInfo{ + inputs: []regMask{buildReg("R16"), gp}, + clobbers: buildReg("R16 FLAGS"), + }, + }, + + // large move + // arg0 = address of dst memory (in R17 aka arm64.REGRT2, changed as side effect) + // arg1 = address of src memory (in R16 aka arm64.REGRT1, changed as side effect) + // arg2 = address of the last element of src + // arg3 = mem + // auxint = alignment + // returns mem + // MOVD.P 8(R16), Rtmp + // MOVD.P Rtmp, 8(R17) + // CMP Rarg2, R16 + // BLE -3(PC) + // Note: the-end-of-src may be not a valid pointer. it's a problem if it is spilled. + // the-end-of-src - 8 is within the area to copy, ok to spill. + { + name: "LoweredMove", + aux: "Int64", + argLength: 4, + reg: regInfo{ + inputs: []regMask{buildReg("R17"), buildReg("R16"), gp}, + clobbers: buildReg("R16 R17 FLAGS"), + }, + }, + // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, // and sorts it to the very beginning of the block to prevent other // use of R26 (arm64.REGCTXT, the closure pointer) diff --git a/src/cmd/compile/internal/ssa/gen/genericOps.go b/src/cmd/compile/internal/ssa/gen/genericOps.go index c0bed93372..c36aea7024 100644 --- a/src/cmd/compile/internal/ssa/gen/genericOps.go +++ b/src/cmd/compile/internal/ssa/gen/genericOps.go @@ -312,8 +312,8 @@ var genericOps = []opData{ // Memory operations {name: "Load", argLength: 2}, // Load from arg0. arg1=memory {name: "Store", argLength: 3, typ: "Mem", aux: "Int64"}, // Store arg1 to arg0. arg2=memory, auxint=size. Returns memory. - {name: "Move", argLength: 3, aux: "Int64"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory. - {name: "Zero", argLength: 2, aux: "Int64"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory. + {name: "Move", argLength: 3, typ: "Mem", aux: "Int64"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory. + {name: "Zero", argLength: 2, typ: "Mem", aux: "Int64"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory. // Function calls. Arguments to the call have already been written to the stack. // Return values appear on the stack. The method receiver, if any, is treated diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index e78623eef2..89a79ef1c0 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -802,6 +802,11 @@ const ( OpARM64SUB OpARM64SUBconst OpARM64MUL + OpARM64MULW + OpARM64MULH + OpARM64UMULH + OpARM64MULL + OpARM64UMULL OpARM64DIV OpARM64UDIV OpARM64DIVW @@ -831,6 +836,14 @@ const ( OpARM64FNEGS OpARM64FNEGD OpARM64FSQRTD + OpARM64SLL + OpARM64SLLconst + OpARM64SRL + OpARM64SRLconst + OpARM64SRA + OpARM64SRAconst + OpARM64RORconst + OpARM64RORWconst OpARM64CMP OpARM64CMPconst OpARM64CMPW @@ -885,6 +898,7 @@ const ( OpARM64FCVTZUD OpARM64FCVTSD OpARM64FCVTDS + OpARM64CSELULT OpARM64CALLstatic OpARM64CALLclosure OpARM64CALLdefer @@ -901,6 +915,9 @@ const ( OpARM64LessEqualU OpARM64GreaterThanU OpARM64GreaterEqualU + OpARM64DUFFZERO + OpARM64LoweredZero + OpARM64LoweredMove OpARM64LoweredGetClosurePtr OpARM64MOVDconvert OpARM64FlagEQ @@ -9969,25 +9986,25 @@ var opcodeTable = [...]opInfo{ asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ADDconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741823}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP + {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -9997,25 +10014,25 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "SUBconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10026,11 +10043,86 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "MULW", + argLen: 2, + commutative: true, + asm: arm64.AMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "MULH", + argLen: 2, + commutative: true, + asm: arm64.ASMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "UMULH", + argLen: 2, + commutative: true, + asm: arm64.AUMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "MULL", + argLen: 2, + commutative: true, + asm: arm64.ASMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "UMULL", + argLen: 2, + commutative: true, + asm: arm64.AUMULL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10040,11 +10132,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10054,11 +10146,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10068,11 +10160,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10082,11 +10174,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUDIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10096,11 +10188,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.AREM, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10110,11 +10202,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10124,11 +10216,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10138,11 +10230,11 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10269,25 +10361,25 @@ var opcodeTable = [...]opInfo{ asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ANDconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10298,25 +10390,25 @@ var opcodeTable = [...]opInfo{ asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "ORconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10327,25 +10419,25 @@ var opcodeTable = [...]opInfo{ asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "XORconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10355,25 +10447,25 @@ var opcodeTable = [...]opInfo{ asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, { name: "BICconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10383,10 +10475,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10396,10 +10488,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10442,14 +10534,126 @@ var opcodeTable = [...]opInfo{ }, }, }, + { + name: "SLL", + argLen: 2, + asm: arm64.ALSL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "SLLconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ALSL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "SRL", + argLen: 2, + asm: arm64.ALSR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "SRLconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ALSR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "SRA", + argLen: 2, + asm: arm64.AASR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "SRAconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AASR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "RORconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AROR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "RORWconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ARORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, { name: "CMP", argLen: 2, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10458,12 +10662,12 @@ var opcodeTable = [...]opInfo{ }, { name: "CMPconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10476,8 +10680,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10491,7 +10695,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10504,8 +10708,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10514,12 +10718,12 @@ var opcodeTable = [...]opInfo{ }, { name: "CMNconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 1, asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10532,8 +10736,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10547,7 +10751,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ {0, 4611686018427387904}, // FLAGS @@ -10584,13 +10788,13 @@ var opcodeTable = [...]opInfo{ }, { name: "MOVDconst", - auxType: auxInt32, + auxType: auxInt64, argLen: 0, rematerializeable: true, asm: arm64.AMOVD, reg: regInfo{ outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10629,7 +10833,7 @@ var opcodeTable = [...]opInfo{ {0, 9223372037391646720}, // SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10640,10 +10844,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10654,10 +10858,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10668,10 +10872,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10682,10 +10886,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10696,10 +10900,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10710,10 +10914,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10724,10 +10928,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10738,7 +10942,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10752,7 +10956,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10766,8 +10970,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, @@ -10778,8 +10982,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, @@ -10790,8 +10994,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, @@ -10802,8 +11006,8 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {1, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, @@ -10815,7 +11019,7 @@ var opcodeTable = [...]opInfo{ reg: regInfo{ inputs: []inputInfo{ {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, @@ -10827,7 +11031,7 @@ var opcodeTable = [...]opInfo{ reg: regInfo{ inputs: []inputInfo{ {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 - {0, 9223372037928517631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 SP SB + {0, 9223372037659820031}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB }, }, }, @@ -10837,10 +11041,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10850,10 +11054,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10863,10 +11067,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10876,10 +11080,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10889,10 +11093,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10902,10 +11106,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10915,10 +11119,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -10928,7 +11132,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10941,7 +11145,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10954,7 +11158,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10967,7 +11171,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10980,7 +11184,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -10993,7 +11197,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -11006,7 +11210,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -11019,7 +11223,7 @@ var opcodeTable = [...]opInfo{ asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, outputs: []outputInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 @@ -11035,7 +11239,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11048,7 +11252,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11061,7 +11265,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11074,7 +11278,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11087,7 +11291,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11100,7 +11304,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11113,7 +11317,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11126,7 +11330,7 @@ var opcodeTable = [...]opInfo{ {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11156,12 +11360,27 @@ var opcodeTable = [...]opInfo{ }, }, }, + { + name: "CSELULT", + argLen: 3, + asm: arm64.ACSEL, + reg: regInfo{ + inputs: []inputInfo{ + {2, 4611686018427387904}, // FLAGS + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + outputs: []outputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, reg: regInfo{ - clobbers: 4899916394042228735, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS + clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS }, }, { @@ -11171,9 +11390,9 @@ var opcodeTable = [...]opInfo{ reg: regInfo{ inputs: []inputInfo{ {1, 67108864}, // R26 - {0, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 SP + {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 SP }, - clobbers: 4899916394042228735, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS + clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS }, }, { @@ -11181,7 +11400,7 @@ var opcodeTable = [...]opInfo{ auxType: auxInt64, argLen: 1, reg: regInfo{ - clobbers: 4899916394042228735, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS + clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS }, }, { @@ -11189,7 +11408,7 @@ var opcodeTable = [...]opInfo{ auxType: auxInt64, argLen: 1, reg: regInfo{ - clobbers: 4899916394042228735, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS + clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS }, }, { @@ -11198,9 +11417,9 @@ var opcodeTable = [...]opInfo{ argLen: 2, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, - clobbers: 4899916394042228735, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS + clobbers: 4899916393773531135, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 FLAGS }, }, { @@ -11208,7 +11427,7 @@ var opcodeTable = [...]opInfo{ argLen: 2, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, }, }, @@ -11220,7 +11439,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11232,7 +11451,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11244,7 +11463,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11256,7 +11475,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11268,7 +11487,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11280,7 +11499,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11292,7 +11511,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11304,7 +11523,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11316,7 +11535,7 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -11328,8 +11547,44 @@ var opcodeTable = [...]opInfo{ {0, 4611686018427387904}, // FLAGS }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + clobbers: 65536, // R16 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65536}, // R16 + {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 + }, + clobbers: 4611686018427453440, // R16 FLAGS + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + reg: regInfo{ + inputs: []inputInfo{ + {0, 131072}, // R17 + {1, 65536}, // R16 + {2, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, + clobbers: 4611686018427584512, // R16 R17 FLAGS }, }, { @@ -11347,10 +11602,10 @@ var opcodeTable = [...]opInfo{ asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 536870911}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 g R29 + {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R29 + {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 }, }, }, @@ -14031,7 +14286,7 @@ var registersARM64 = [...]Register{ {62, "FLAGS"}, {63, "SB"}, } -var gpRegMaskARM64 = regMask(402653183) +var gpRegMaskARM64 = regMask(133955583) var fpRegMaskARM64 = regMask(288230375077969920) var flagRegMaskARM64 = regMask(4611686018427387904) var framepointerRegARM64 = int8(-1) diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go index 2bee7c1916..150a318cdc 100644 --- a/src/cmd/compile/internal/ssa/regalloc.go +++ b/src/cmd/compile/internal/ssa/regalloc.go @@ -486,6 +486,8 @@ func (s *regAllocState) init(f *Func) { s.allocatable &^= 1 << 15 // R15 case "arm": s.allocatable &^= 1 << 9 // R9 + case "arm64": + // nothing to do? default: s.f.Config.fe.Unimplementedf(0, "arch %s not implemented", s.f.Config.arch) } diff --git a/src/cmd/compile/internal/ssa/rewrite.go b/src/cmd/compile/internal/ssa/rewrite.go index 3368d8fff5..082aacd9c9 100644 --- a/src/cmd/compile/internal/ssa/rewrite.go +++ b/src/cmd/compile/internal/ssa/rewrite.go @@ -304,6 +304,19 @@ func duffAMD64(size int64) (int64, int64) { return off, adj } +// moveSize returns the number of bytes an aligned MOV instruction moves +func moveSize(align int64, c *Config) int64 { + switch { + case align%8 == 0 && c.IntSize == 8: + return 8 + case align%4 == 0: + return 4 + case align%2 == 0: + return 2 + } + return 1 +} + // mergePoint finds a block among a's blocks which dominates b and is itself // dominated by all of a's blocks. Returns nil if it can't find one. // Might return nil even if one does exist. diff --git a/src/cmd/compile/internal/ssa/rewriteARM64.go b/src/cmd/compile/internal/ssa/rewriteARM64.go index 72717f66be..ecde744d0f 100644 --- a/src/cmd/compile/internal/ssa/rewriteARM64.go +++ b/src/cmd/compile/internal/ssa/rewriteARM64.go @@ -36,6 +36,8 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpAnd8(v, config) case OpAndB: return rewriteValueARM64_OpAndB(v, config) + case OpAvg64u: + return rewriteValueARM64_OpAvg64u(v, config) case OpClosureCall: return rewriteValueARM64_OpClosureCall(v, config) case OpCom16: @@ -182,6 +184,22 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpGreater8(v, config) case OpGreater8U: return rewriteValueARM64_OpGreater8U(v, config) + case OpHmul16: + return rewriteValueARM64_OpHmul16(v, config) + case OpHmul16u: + return rewriteValueARM64_OpHmul16u(v, config) + case OpHmul32: + return rewriteValueARM64_OpHmul32(v, config) + case OpHmul32u: + return rewriteValueARM64_OpHmul32u(v, config) + case OpHmul64: + return rewriteValueARM64_OpHmul64(v, config) + case OpHmul64u: + return rewriteValueARM64_OpHmul64u(v, config) + case OpHmul8: + return rewriteValueARM64_OpHmul8(v, config) + case OpHmul8u: + return rewriteValueARM64_OpHmul8u(v, config) case OpInterCall: return rewriteValueARM64_OpInterCall(v, config) case OpIsInBounds: @@ -232,6 +250,46 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpLess8U(v, config) case OpLoad: return rewriteValueARM64_OpLoad(v, config) + case OpLrot16: + return rewriteValueARM64_OpLrot16(v, config) + case OpLrot32: + return rewriteValueARM64_OpLrot32(v, config) + case OpLrot64: + return rewriteValueARM64_OpLrot64(v, config) + case OpLrot8: + return rewriteValueARM64_OpLrot8(v, config) + case OpLsh16x16: + return rewriteValueARM64_OpLsh16x16(v, config) + case OpLsh16x32: + return rewriteValueARM64_OpLsh16x32(v, config) + case OpLsh16x64: + return rewriteValueARM64_OpLsh16x64(v, config) + case OpLsh16x8: + return rewriteValueARM64_OpLsh16x8(v, config) + case OpLsh32x16: + return rewriteValueARM64_OpLsh32x16(v, config) + case OpLsh32x32: + return rewriteValueARM64_OpLsh32x32(v, config) + case OpLsh32x64: + return rewriteValueARM64_OpLsh32x64(v, config) + case OpLsh32x8: + return rewriteValueARM64_OpLsh32x8(v, config) + case OpLsh64x16: + return rewriteValueARM64_OpLsh64x16(v, config) + case OpLsh64x32: + return rewriteValueARM64_OpLsh64x32(v, config) + case OpLsh64x64: + return rewriteValueARM64_OpLsh64x64(v, config) + case OpLsh64x8: + return rewriteValueARM64_OpLsh64x8(v, config) + case OpLsh8x16: + return rewriteValueARM64_OpLsh8x16(v, config) + case OpLsh8x32: + return rewriteValueARM64_OpLsh8x32(v, config) + case OpLsh8x64: + return rewriteValueARM64_OpLsh8x64(v, config) + case OpLsh8x8: + return rewriteValueARM64_OpLsh8x8(v, config) case OpARM64MOVBUload: return rewriteValueARM64_OpARM64MOVBUload(v, config) case OpARM64MOVBload: @@ -270,6 +328,8 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpMod8(v, config) case OpMod8u: return rewriteValueARM64_OpMod8u(v, config) + case OpMove: + return rewriteValueARM64_OpMove(v, config) case OpMul16: return rewriteValueARM64_OpMul16(v, config) case OpMul32: @@ -326,6 +386,70 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpOr8(v, config) case OpOrB: return rewriteValueARM64_OpOrB(v, config) + case OpRsh16Ux16: + return rewriteValueARM64_OpRsh16Ux16(v, config) + case OpRsh16Ux32: + return rewriteValueARM64_OpRsh16Ux32(v, config) + case OpRsh16Ux64: + return rewriteValueARM64_OpRsh16Ux64(v, config) + case OpRsh16Ux8: + return rewriteValueARM64_OpRsh16Ux8(v, config) + case OpRsh16x16: + return rewriteValueARM64_OpRsh16x16(v, config) + case OpRsh16x32: + return rewriteValueARM64_OpRsh16x32(v, config) + case OpRsh16x64: + return rewriteValueARM64_OpRsh16x64(v, config) + case OpRsh16x8: + return rewriteValueARM64_OpRsh16x8(v, config) + case OpRsh32Ux16: + return rewriteValueARM64_OpRsh32Ux16(v, config) + case OpRsh32Ux32: + return rewriteValueARM64_OpRsh32Ux32(v, config) + case OpRsh32Ux64: + return rewriteValueARM64_OpRsh32Ux64(v, config) + case OpRsh32Ux8: + return rewriteValueARM64_OpRsh32Ux8(v, config) + case OpRsh32x16: + return rewriteValueARM64_OpRsh32x16(v, config) + case OpRsh32x32: + return rewriteValueARM64_OpRsh32x32(v, config) + case OpRsh32x64: + return rewriteValueARM64_OpRsh32x64(v, config) + case OpRsh32x8: + return rewriteValueARM64_OpRsh32x8(v, config) + case OpRsh64Ux16: + return rewriteValueARM64_OpRsh64Ux16(v, config) + case OpRsh64Ux32: + return rewriteValueARM64_OpRsh64Ux32(v, config) + case OpRsh64Ux64: + return rewriteValueARM64_OpRsh64Ux64(v, config) + case OpRsh64Ux8: + return rewriteValueARM64_OpRsh64Ux8(v, config) + case OpRsh64x16: + return rewriteValueARM64_OpRsh64x16(v, config) + case OpRsh64x32: + return rewriteValueARM64_OpRsh64x32(v, config) + case OpRsh64x64: + return rewriteValueARM64_OpRsh64x64(v, config) + case OpRsh64x8: + return rewriteValueARM64_OpRsh64x8(v, config) + case OpRsh8Ux16: + return rewriteValueARM64_OpRsh8Ux16(v, config) + case OpRsh8Ux32: + return rewriteValueARM64_OpRsh8Ux32(v, config) + case OpRsh8Ux64: + return rewriteValueARM64_OpRsh8Ux64(v, config) + case OpRsh8Ux8: + return rewriteValueARM64_OpRsh8Ux8(v, config) + case OpRsh8x16: + return rewriteValueARM64_OpRsh8x16(v, config) + case OpRsh8x32: + return rewriteValueARM64_OpRsh8x32(v, config) + case OpRsh8x64: + return rewriteValueARM64_OpRsh8x64(v, config) + case OpRsh8x8: + return rewriteValueARM64_OpRsh8x8(v, config) case OpSignExt16to32: return rewriteValueARM64_OpSignExt16to32(v, config) case OpSignExt16to64: @@ -338,6 +462,8 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpSignExt8to32(v, config) case OpSignExt8to64: return rewriteValueARM64_OpSignExt8to64(v, config) + case OpSqrt: + return rewriteValueARM64_OpSqrt(v, config) case OpStaticCall: return rewriteValueARM64_OpStaticCall(v, config) case OpStore: @@ -376,6 +502,8 @@ func rewriteValueARM64(v *Value, config *Config) bool { return rewriteValueARM64_OpXor64(v, config) case OpXor8: return rewriteValueARM64_OpXor8(v, config) + case OpZero: + return rewriteValueARM64_OpZero(v, config) case OpZeroExt16to32: return rewriteValueARM64_OpZeroExt16to32(v, config) case OpZeroExt16to64: @@ -609,6 +737,39 @@ func rewriteValueARM64_OpAndB(v *Value, config *Config) bool { return true } } +func rewriteValueARM64_OpAvg64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Avg64u x y) + // cond: + // result: (ADD (ADD (SRLconst x [1]) (SRLconst y [1])) (AND (AND x y) (MOVDconst [1]))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64ADD) + v0 := b.NewValue0(v.Line, OpARM64ADD, t) + v1 := b.NewValue0(v.Line, OpARM64SRLconst, t) + v1.AddArg(x) + v1.AuxInt = 1 + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64SRLconst, t) + v2.AddArg(y) + v2.AuxInt = 1 + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpARM64AND, t) + v4 := b.NewValue0(v.Line, OpARM64AND, t) + v4.AddArg(x) + v4.AddArg(y) + v3.AddArg(v4) + v5 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v5.AuxInt = 1 + v3.AddArg(v5) + v.AddArg(v3) + return true + } +} func rewriteValueARM64_OpClosureCall(v *Value, config *Config) bool { b := v.Block _ = b @@ -1276,16 +1437,18 @@ func rewriteValueARM64_OpEqB(v *Value, config *Config) bool { _ = b // match: (EqB x y) // cond: - // result: (XORconst [1] (XOR x y)) + // result: (XOR (MOVDconst [1]) (XOR x y)) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64XORconst) - v.AuxInt = 1 - v0 := b.NewValue0(v.Line, OpARM64XOR, config.fe.TypeBool()) - v0.AddArg(x) - v0.AddArg(y) + v.reset(OpARM64XOR) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 1 v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64XOR, config.fe.TypeBool()) + v1.AddArg(x) + v1.AddArg(y) + v.AddArg(v1) return true } } @@ -1908,6 +2071,160 @@ func rewriteValueARM64_OpGreater8U(v *Value, config *Config) bool { return true } } +func rewriteValueARM64_OpHmul16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul16 x y) + // cond: + // result: (SRAconst (MULW (SignExt16to32 x) (SignExt16to32 y)) [16]) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpARM64MULW, config.fe.TypeInt32()) + v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v.AuxInt = 16 + return true + } +} +func rewriteValueARM64_OpHmul16u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul16u x y) + // cond: + // result: (SRLconst (MUL (ZeroExt16to32 x) (ZeroExt16to32 y)) [16]) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64SRLconst) + v0 := b.NewValue0(v.Line, OpARM64MUL, config.fe.TypeUInt32()) + v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v.AuxInt = 16 + return true + } +} +func rewriteValueARM64_OpHmul32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul32 x y) + // cond: + // result: (SRAconst (MULL x y) [32]) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpARM64MULL, config.fe.TypeInt64()) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AuxInt = 32 + return true + } +} +func rewriteValueARM64_OpHmul32u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul32u x y) + // cond: + // result: (SRAconst (UMULL x y) [32]) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpARM64UMULL, config.fe.TypeUInt64()) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v.AuxInt = 32 + return true + } +} +func rewriteValueARM64_OpHmul64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul64 x y) + // cond: + // result: (MULH x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MULH) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpHmul64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul64u x y) + // cond: + // result: (UMULH x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64UMULH) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpHmul8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul8 x y) + // cond: + // result: (SRAconst (MULW (SignExt8to32 x) (SignExt8to32 y)) [8]) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpARM64MULW, config.fe.TypeInt16()) + v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v.AuxInt = 8 + return true + } +} +func rewriteValueARM64_OpHmul8u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Hmul8u x y) + // cond: + // result: (SRLconst (MUL (ZeroExt8to32 x) (ZeroExt8to32 y)) [8]) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64SRLconst) + v0 := b.NewValue0(v.Line, OpARM64MUL, config.fe.TypeUInt16()) + v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v.AuxInt = 8 + return true + } +} func rewriteValueARM64_OpInterCall(v *Value, config *Config) bool { b := v.Block _ = b @@ -2502,385 +2819,694 @@ func rewriteValueARM64_OpLoad(v *Value, config *Config) bool { } return false } -func rewriteValueARM64_OpARM64MOVBUload(v *Value, config *Config) bool { +func rewriteValueARM64_OpLrot16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (Lrot16 x [c]) // cond: - // result: (MOVBUload [off1+off2] {sym} ptr mem) + // result: (OR (SLLconst x [c&15]) (SRLconst (ZeroExt16to64 x) [16-c&15])) for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { - break - } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - mem := v.Args[1] - v.reset(OpARM64MOVBUload) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(mem) + t := v.Type + x := v.Args[0] + c := v.AuxInt + v.reset(OpARM64OR) + v0 := b.NewValue0(v.Line, OpARM64SLLconst, t) + v0.AddArg(x) + v0.AuxInt = c & 15 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64SRLconst, t) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v2.AddArg(x) + v1.AddArg(v2) + v1.AuxInt = 16 - c&15 + v.AddArg(v1) return true } - // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) +} +func rewriteValueARM64_OpLrot32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lrot32 x [c]) + // cond: + // result: (RORWconst x [32-c&31]) for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - mem := v.Args[1] - if !(canMergeSym(sym1, sym2)) { - break - } - v.reset(OpARM64MOVBUload) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(mem) + x := v.Args[0] + c := v.AuxInt + v.reset(OpARM64RORWconst) + v.AddArg(x) + v.AuxInt = 32 - c&31 return true } - return false } -func rewriteValueARM64_OpARM64MOVBload(v *Value, config *Config) bool { +func rewriteValueARM64_OpLrot64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (Lrot64 x [c]) // cond: - // result: (MOVBload [off1+off2] {sym} ptr mem) + // result: (RORconst x [64-c&63]) for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { - break - } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - mem := v.Args[1] - v.reset(OpARM64MOVBload) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(mem) + x := v.Args[0] + c := v.AuxInt + v.reset(OpARM64RORconst) + v.AddArg(x) + v.AuxInt = 64 - c&63 return true } - // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) +} +func rewriteValueARM64_OpLrot8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lrot8 x [c]) + // cond: + // result: (OR (SLLconst x [c&7]) (SRLconst (ZeroExt8to64 x) [8-c&7])) for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - mem := v.Args[1] - if !(canMergeSym(sym1, sym2)) { - break - } - v.reset(OpARM64MOVBload) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(mem) + t := v.Type + x := v.Args[0] + c := v.AuxInt + v.reset(OpARM64OR) + v0 := b.NewValue0(v.Line, OpARM64SLLconst, t) + v0.AddArg(x) + v0.AuxInt = c & 7 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64SRLconst, t) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(x) + v1.AddArg(v2) + v1.AuxInt = 8 - c&7 + v.AddArg(v1) return true } - return false } -func rewriteValueARM64_OpARM64MOVBstore(v *Value, config *Config) bool { +func rewriteValueARM64_OpLsh16x16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // match: (Lsh16x16 x y) // cond: - // result: (MOVBstore [off1+off2] {sym} ptr val mem) + // result: (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { - break - } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] - v.reset(OpARM64MOVBstore) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(val) - v.AddArg(mem) - return true - } - // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) - for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] - if !(canMergeSym(sym1, sym2)) { - break - } - v.reset(OpARM64MOVBstore) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(val) - v.AddArg(mem) + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } - return false } -func rewriteValueARM64_OpARM64MOVDload(v *Value, config *Config) bool { +func rewriteValueARM64_OpLsh16x32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (Lsh16x32 x y) // cond: - // result: (MOVDload [off1+off2] {sym} ptr mem) - for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { - break - } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - mem := v.Args[1] - v.reset(OpARM64MOVDload) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(mem) - return true - } - // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + // result: (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - mem := v.Args[1] - if !(canMergeSym(sym1, sym2)) { - break - } - v.reset(OpARM64MOVDload) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(mem) + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } - return false } -func rewriteValueARM64_OpARM64MOVDstore(v *Value, config *Config) bool { +func rewriteValueARM64_OpLsh16x64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) - // cond: - // result: (MOVDstore [off1+off2] {sym} ptr val mem) + // match: (Lsh16x64 x (MOVDconst [c])) + // cond: uint64(c) < 16 + // result: (SLLconst x [c]) for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { break } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] - v.reset(OpARM64MOVDstore) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(val) - v.AddArg(mem) + c := v_1.AuxInt + if !(uint64(c) < 16) { + break + } + v.reset(OpARM64SLLconst) + v.AddArg(x) + v.AuxInt = c return true } - // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + // match: (Lsh16x64 _ (MOVDconst [c])) + // cond: uint64(c) >= 16 + // result: (MOVDconst [0]) for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { break } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] - if !(canMergeSym(sym1, sym2)) { + c := v_1.AuxInt + if !(uint64(c) >= 16) { break } - v.reset(OpARM64MOVDstore) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(val) - v.AddArg(mem) + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 + return true + } + // match: (Lsh16x64 x y) + // cond: + // result: (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v2.AuxInt = 64 + v2.AddArg(y) + v.AddArg(v2) return true } - return false } -func rewriteValueARM64_OpARM64MOVHUload(v *Value, config *Config) bool { +func rewriteValueARM64_OpLsh16x8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (Lsh16x8 x y) // cond: - // result: (MOVHUload [off1+off2] {sym} ptr mem) + // result: (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { - break - } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - mem := v.Args[1] - v.reset(OpARM64MOVHUload) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(mem) + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } - // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) +} +func rewriteValueARM64_OpLsh32x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x16 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { - break - } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - mem := v.Args[1] - if !(canMergeSym(sym1, sym2)) { - break - } - v.reset(OpARM64MOVHUload) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(mem) + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } - return false } -func rewriteValueARM64_OpARM64MOVHload(v *Value, config *Config) bool { +func rewriteValueARM64_OpLsh32x32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (Lsh32x32 x y) // cond: - // result: (MOVHload [off1+off2] {sym} ptr mem) + // result: (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { - off1 := v.AuxInt - sym := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64ADDconst { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh32x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x64 x (MOVDconst [c])) + // cond: uint64(c) < 32 + // result: (SLLconst x [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { break } - off2 := v_0.AuxInt - ptr := v_0.Args[0] - mem := v.Args[1] - v.reset(OpARM64MOVHload) - v.AuxInt = off1 + off2 - v.Aux = sym - v.AddArg(ptr) - v.AddArg(mem) + c := v_1.AuxInt + if !(uint64(c) < 32) { + break + } + v.reset(OpARM64SLLconst) + v.AddArg(x) + v.AuxInt = c return true } - // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) - // cond: canMergeSym(sym1,sym2) - // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + // match: (Lsh32x64 _ (MOVDconst [c])) + // cond: uint64(c) >= 32 + // result: (MOVDconst [0]) for { - off1 := v.AuxInt - sym1 := v.Aux - v_0 := v.Args[0] - if v_0.Op != OpARM64MOVDaddr { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { break } - off2 := v_0.AuxInt - sym2 := v_0.Aux - ptr := v_0.Args[0] - mem := v.Args[1] - if !(canMergeSym(sym1, sym2)) { + c := v_1.AuxInt + if !(uint64(c) >= 32) { break } - v.reset(OpARM64MOVHload) - v.AuxInt = off1 + off2 - v.Aux = mergeSym(sym1, sym2) - v.AddArg(ptr) - v.AddArg(mem) + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 return true } - return false -} -func rewriteValueARM64_OpARM64MOVHstore(v *Value, config *Config) bool { - b := v.Block - _ = b - // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // match: (Lsh32x64 x y) // cond: - // result: (MOVHstore [off1+off2] {sym} ptr val mem) + // result: (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) for { - off1 := v.AuxInt - sym := v.Aux + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v2.AuxInt = 64 + v2.AddArg(y) + v.AddArg(v2) + return true + } +} +func rewriteValueARM64_OpLsh32x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh32x8 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh64x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x16 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh64x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x32 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh64x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x64 x (MOVDconst [c])) + // cond: uint64(c) < 64 + // result: (SLLconst x [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 64) { + break + } + v.reset(OpARM64SLLconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (Lsh64x64 _ (MOVDconst [c])) + // cond: uint64(c) >= 64 + // result: (MOVDconst [0]) + for { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 64) { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 + return true + } + // match: (Lsh64x64 x y) + // cond: + // result: (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v2.AuxInt = 64 + v2.AddArg(y) + v.AddArg(v2) + return true + } +} +func rewriteValueARM64_OpLsh64x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh64x8 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh8x16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x16 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh8x32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x32 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpLsh8x64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x64 x (MOVDconst [c])) + // cond: uint64(c) < 8 + // result: (SLLconst x [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 8) { + break + } + v.reset(OpARM64SLLconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (Lsh8x64 _ (MOVDconst [c])) + // cond: uint64(c) >= 8 + // result: (MOVDconst [0]) + for { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 8) { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 + return true + } + // match: (Lsh8x64 x y) + // cond: + // result: (CSELULT (SLL x y) (Const64 [0]) (CMPconst [64] y)) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v2.AuxInt = 64 + v2.AddArg(y) + v.AddArg(v2) + return true + } +} +func rewriteValueARM64_OpLsh8x8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Lsh8x8 x y) + // cond: + // result: (CSELULT (SLL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) + for { + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SLL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) + return true + } +} +func rewriteValueARM64_OpARM64MOVBUload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: + // result: (MOVBUload [off1+off2] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux v_0 := v.Args[0] if v_0.Op != OpARM64ADDconst { break } off2 := v_0.AuxInt ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] - v.reset(OpARM64MOVHstore) + mem := v.Args[1] + v.reset(OpARM64MOVBUload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) - v.AddArg(val) v.AddArg(mem) return true } - // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + // match: (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + // result: (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux @@ -2891,27 +3517,25 @@ func rewriteValueARM64_OpARM64MOVHstore(v *Value, config *Config) bool { off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] + mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } - v.reset(OpARM64MOVHstore) + v.reset(OpARM64MOVBUload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) - v.AddArg(val) v.AddArg(mem) return true } return false } -func rewriteValueARM64_OpARM64MOVWUload(v *Value, config *Config) bool { +func rewriteValueARM64_OpARM64MOVBload(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: - // result: (MOVWUload [off1+off2] {sym} ptr mem) + // result: (MOVBload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux @@ -2922,16 +3546,16 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value, config *Config) bool { off2 := v_0.AuxInt ptr := v_0.Args[0] mem := v.Args[1] - v.reset(OpARM64MOVWUload) + v.reset(OpARM64MOVBload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) v.AddArg(mem) return true } - // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + // result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux @@ -2946,7 +3570,7 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value, config *Config) bool { if !(canMergeSym(sym1, sym2)) { break } - v.reset(OpARM64MOVWUload) + v.reset(OpARM64MOVBload) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) @@ -2955,12 +3579,12 @@ func rewriteValueARM64_OpARM64MOVWUload(v *Value, config *Config) bool { } return false } -func rewriteValueARM64_OpARM64MOVWload(v *Value, config *Config) bool { +func rewriteValueARM64_OpARM64MOVBstore(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) + // match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) // cond: - // result: (MOVWload [off1+off2] {sym} ptr mem) + // result: (MOVBstore [off1+off2] {sym} ptr val mem) for { off1 := v.AuxInt sym := v.Aux @@ -2970,17 +3594,19 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value, config *Config) bool { } off2 := v_0.AuxInt ptr := v_0.Args[0] - mem := v.Args[1] - v.reset(OpARM64MOVWload) + val := v.Args[1] + mem := v.Args[2] + v.reset(OpARM64MOVBstore) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) + v.AddArg(val) v.AddArg(mem) return true } - // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // match: (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + // result: (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) for { off1 := v.AuxInt sym1 := v.Aux @@ -2991,25 +3617,27 @@ func rewriteValueARM64_OpARM64MOVWload(v *Value, config *Config) bool { off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] - mem := v.Args[1] + val := v.Args[1] + mem := v.Args[2] if !(canMergeSym(sym1, sym2)) { break } - v.reset(OpARM64MOVWload) + v.reset(OpARM64MOVBstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) + v.AddArg(val) v.AddArg(mem) return true } return false } -func rewriteValueARM64_OpARM64MOVWstore(v *Value, config *Config) bool { +func rewriteValueARM64_OpARM64MOVDload(v *Value, config *Config) bool { b := v.Block _ = b - // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) // cond: - // result: (MOVWstore [off1+off2] {sym} ptr val mem) + // result: (MOVDload [off1+off2] {sym} ptr mem) for { off1 := v.AuxInt sym := v.Aux @@ -3019,19 +3647,17 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value, config *Config) bool { } off2 := v_0.AuxInt ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] - v.reset(OpARM64MOVWstore) + mem := v.Args[1] + v.reset(OpARM64MOVDload) v.AuxInt = off1 + off2 v.Aux = sym v.AddArg(ptr) - v.AddArg(val) v.AddArg(mem) return true } - // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + // match: (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) // cond: canMergeSym(sym1,sym2) - // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + // result: (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) for { off1 := v.AuxInt sym1 := v.Aux @@ -3042,12 +3668,214 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value, config *Config) bool { off2 := v_0.AuxInt sym2 := v_0.Aux ptr := v_0.Args[0] - val := v.Args[1] - mem := v.Args[2] + mem := v.Args[1] if !(canMergeSym(sym1, sym2)) { break } - v.reset(OpARM64MOVWstore) + v.reset(OpARM64MOVDload) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64MOVDstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // cond: + // result: (MOVDstore [off1+off2] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpARM64MOVDstore) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVDstore) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64MOVHUload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: + // result: (MOVHUload [off1+off2] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + mem := v.Args[1] + v.reset(OpARM64MOVHUload) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVHUload) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64MOVHload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: + // result: (MOVHload [off1+off2] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + mem := v.Args[1] + v.reset(OpARM64MOVHload) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVHload) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64MOVHstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // cond: + // result: (MOVHstore [off1+off2] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpARM64MOVHstore) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVHstore) v.AuxInt = off1 + off2 v.Aux = mergeSym(sym1, sym2) v.AddArg(ptr) @@ -3055,584 +3883,2446 @@ func rewriteValueARM64_OpARM64MOVWstore(v *Value, config *Config) bool { v.AddArg(mem) return true } - return false + return false +} +func rewriteValueARM64_OpARM64MOVWUload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: + // result: (MOVWUload [off1+off2] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + mem := v.Args[1] + v.reset(OpARM64MOVWUload) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVWUload) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64MOVWload(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) + // cond: + // result: (MOVWload [off1+off2] {sym} ptr mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + mem := v.Args[1] + v.reset(OpARM64MOVWload) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + mem := v.Args[1] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVWload) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpARM64MOVWstore(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) + // cond: + // result: (MOVWstore [off1+off2] {sym} ptr val mem) + for { + off1 := v.AuxInt + sym := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64ADDconst { + break + } + off2 := v_0.AuxInt + ptr := v_0.Args[0] + val := v.Args[1] + mem := v.Args[2] + v.reset(OpARM64MOVWstore) + v.AuxInt = off1 + off2 + v.Aux = sym + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + // match: (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) + // cond: canMergeSym(sym1,sym2) + // result: (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) + for { + off1 := v.AuxInt + sym1 := v.Aux + v_0 := v.Args[0] + if v_0.Op != OpARM64MOVDaddr { + break + } + off2 := v_0.AuxInt + sym2 := v_0.Aux + ptr := v_0.Args[0] + val := v.Args[1] + mem := v.Args[2] + if !(canMergeSym(sym1, sym2)) { + break + } + v.reset(OpARM64MOVWstore) + v.AuxInt = off1 + off2 + v.Aux = mergeSym(sym1, sym2) + v.AddArg(ptr) + v.AddArg(val) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpMod16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod16 x y) + // cond: + // result: (MODW (SignExt16to32 x) (SignExt16to32 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MODW) + v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32()) + v1.AddArg(y) + v.AddArg(v1) + return true + } +} +func rewriteValueARM64_OpMod16u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod16u x y) + // cond: + // result: (UMODW (ZeroExt16to32 x) (ZeroExt16to32 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64UMODW) + v0 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) + v1.AddArg(y) + v.AddArg(v1) + return true + } +} +func rewriteValueARM64_OpMod32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod32 x y) + // cond: + // result: (MODW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MODW) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMod32u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod32u x y) + // cond: + // result: (UMODW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64UMODW) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMod64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod64 x y) + // cond: + // result: (MOD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MOD) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMod64u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod64u x y) + // cond: + // result: (UMOD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64UMOD) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMod8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod8 x y) + // cond: + // result: (MODW (SignExt8to32 x) (SignExt8to32 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MODW) + v0 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32()) + v1.AddArg(y) + v.AddArg(v1) + return true + } +} +func rewriteValueARM64_OpMod8u(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mod8u x y) + // cond: + // result: (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64UMODW) + v0 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v1.AddArg(y) + v.AddArg(v1) + return true + } +} +func rewriteValueARM64_OpMove(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Move [s] _ _ mem) + // cond: SizeAndAlign(s).Size() == 0 + // result: mem + for { + s := v.AuxInt + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 0) { + break + } + v.reset(OpCopy) + v.Type = mem.Type + v.AddArg(mem) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 1 + // result: (MOVBstore dst (MOVBUload src mem) mem) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 1) { + break + } + v.reset(OpARM64MOVBstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore dst (MOVHUload src mem) mem) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 2 + // result: (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem)) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 2) { + break + } + v.reset(OpARM64MOVBstore) + v.AuxInt = 1 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v0.AuxInt = 1 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 + // result: (MOVWstore dst (MOVWUload src mem) mem) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) { + break + } + v.reset(OpARM64MOVWstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVWUload, config.fe.TypeUInt32()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore [2] dst (MOVHUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem)) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AuxInt = 2 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v0.AuxInt = 2 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 4 + // result: (MOVBstore [3] dst (MOVBUload [3] src mem) (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem)))) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 4) { + break + } + v.reset(OpARM64MOVBstore) + v.AuxInt = 3 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v0.AuxInt = 3 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v1.AuxInt = 2 + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v2.AuxInt = 2 + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v3.AuxInt = 1 + v3.AddArg(dst) + v4 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v4.AuxInt = 1 + v4.AddArg(src) + v4.AddArg(mem) + v3.AddArg(v4) + v5 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v5.AddArg(dst) + v6 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v6.AddArg(src) + v6.AddArg(mem) + v5.AddArg(v6) + v5.AddArg(mem) + v3.AddArg(v5) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 + // result: (MOVDstore dst (MOVDload src mem) mem) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0) { + break + } + v.reset(OpARM64MOVDstore) + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVDload, config.fe.TypeUInt64()) + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 + // result: (MOVWstore [4] dst (MOVWUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem)) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) { + break + } + v.reset(OpARM64MOVWstore) + v.AuxInt = 4 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVWUload, config.fe.TypeUInt32()) + v0.AuxInt = 4 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVWstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVWUload, config.fe.TypeUInt32()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore [6] dst (MOVHUload [6] src mem) (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVHstore [2] dst (MOVHUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem)))) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AuxInt = 6 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v0.AuxInt = 6 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v1.AuxInt = 4 + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v2.AuxInt = 4 + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v3.AuxInt = 2 + v3.AddArg(dst) + v4 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v4.AuxInt = 2 + v4.AddArg(src) + v4.AddArg(mem) + v3.AddArg(v4) + v5 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v5.AddArg(dst) + v6 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v6.AddArg(src) + v6.AddArg(mem) + v5.AddArg(v6) + v5.AddArg(mem) + v3.AddArg(v5) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 3 + // result: (MOVBstore [2] dst (MOVBUload [2] src mem) (MOVBstore [1] dst (MOVBUload [1] src mem) (MOVBstore dst (MOVBUload src mem) mem))) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 3) { + break + } + v.reset(OpARM64MOVBstore) + v.AuxInt = 2 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v0.AuxInt = 2 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v1.AuxInt = 1 + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v2.AuxInt = 1 + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v3.AddArg(dst) + v4 := b.NewValue0(v.Line, OpARM64MOVBUload, config.fe.TypeUInt8()) + v4.AddArg(src) + v4.AddArg(mem) + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore [4] dst (MOVHUload [4] src mem) (MOVHstore [2] dst (MOVHUload [2] src mem) (MOVHstore dst (MOVHUload src mem) mem))) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AuxInt = 4 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v0.AuxInt = 4 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v1.AuxInt = 2 + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v2.AuxInt = 2 + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v3.AddArg(dst) + v4 := b.NewValue0(v.Line, OpARM64MOVHUload, config.fe.TypeUInt16()) + v4.AddArg(src) + v4.AddArg(mem) + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 + // result: (MOVWstore [8] dst (MOVWUload [8] src mem) (MOVWstore [4] dst (MOVWUload [4] src mem) (MOVWstore dst (MOVWUload src mem) mem))) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) { + break + } + v.reset(OpARM64MOVWstore) + v.AuxInt = 8 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVWUload, config.fe.TypeUInt32()) + v0.AuxInt = 8 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVWstore, TypeMem) + v1.AuxInt = 4 + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVWUload, config.fe.TypeUInt32()) + v2.AuxInt = 4 + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVWstore, TypeMem) + v3.AddArg(dst) + v4 := b.NewValue0(v.Line, OpARM64MOVWUload, config.fe.TypeUInt32()) + v4.AddArg(src) + v4.AddArg(mem) + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 + // result: (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0) { + break + } + v.reset(OpARM64MOVDstore) + v.AuxInt = 8 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVDload, config.fe.TypeUInt64()) + v0.AuxInt = 8 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVDstore, TypeMem) + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVDload, config.fe.TypeUInt64()) + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 + // result: (MOVDstore [16] dst (MOVDload [16] src mem) (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem))) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0) { + break + } + v.reset(OpARM64MOVDstore) + v.AuxInt = 16 + v.AddArg(dst) + v0 := b.NewValue0(v.Line, OpARM64MOVDload, config.fe.TypeUInt64()) + v0.AuxInt = 16 + v0.AddArg(src) + v0.AddArg(mem) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVDstore, TypeMem) + v1.AuxInt = 8 + v1.AddArg(dst) + v2 := b.NewValue0(v.Line, OpARM64MOVDload, config.fe.TypeUInt64()) + v2.AuxInt = 8 + v2.AddArg(src) + v2.AddArg(mem) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVDstore, TypeMem) + v3.AddArg(dst) + v4 := b.NewValue0(v.Line, OpARM64MOVDload, config.fe.TypeUInt64()) + v4.AddArg(src) + v4.AddArg(mem) + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Move [s] dst src mem) + // cond: SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0 + // result: (LoweredMove [SizeAndAlign(s).Align()] dst src (ADDconst src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) mem) + for { + s := v.AuxInt + dst := v.Args[0] + src := v.Args[1] + mem := v.Args[2] + if !(SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0) { + break + } + v.reset(OpARM64LoweredMove) + v.AuxInt = SizeAndAlign(s).Align() + v.AddArg(dst) + v.AddArg(src) + v0 := b.NewValue0(v.Line, OpARM64ADDconst, src.Type) + v0.AddArg(src) + v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config) + v.AddArg(v0) + v.AddArg(mem) + return true + } + return false +} +func rewriteValueARM64_OpMul16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul16 x y) + // cond: + // result: (MULW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MULW) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMul32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul32 x y) + // cond: + // result: (MULW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MULW) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMul32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul32F x y) + // cond: + // result: (FMULS x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64FMULS) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMul64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul64 x y) + // cond: + // result: (MUL x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MUL) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMul64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul64F x y) + // cond: + // result: (FMULD x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64FMULD) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpMul8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Mul8 x y) + // cond: + // result: (MULW x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64MULW) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpNeg16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg16 x) + // cond: + // result: (NEG x) + for { + x := v.Args[0] + v.reset(OpARM64NEG) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpNeg32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg32 x) + // cond: + // result: (NEG x) + for { + x := v.Args[0] + v.reset(OpARM64NEG) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpNeg32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg32F x) + // cond: + // result: (FNEGS x) + for { + x := v.Args[0] + v.reset(OpARM64FNEGS) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpNeg64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg64 x) + // cond: + // result: (NEG x) + for { + x := v.Args[0] + v.reset(OpARM64NEG) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpNeg64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg64F x) + // cond: + // result: (FNEGD x) + for { + x := v.Args[0] + v.reset(OpARM64FNEGD) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpNeg8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neg8 x) + // cond: + // result: (NEG x) + for { + x := v.Args[0] + v.reset(OpARM64NEG) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpNeq16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq16 x y) + // cond: + // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64CMPW, TypeFlags) + v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNeq32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq32 x y) + // cond: + // result: (NotEqual (CMPW x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64CMPW, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNeq32F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq32F x y) + // cond: + // result: (NotEqual (FCMPS x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64FCMPS, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNeq64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq64 x y) + // cond: + // result: (NotEqual (CMP x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64CMP, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNeq64F(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq64F x y) + // cond: + // result: (NotEqual (FCMPD x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64FCMPD, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNeq8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Neq8 x y) + // cond: + // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64CMPW, TypeFlags) + v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNeqB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NeqB x y) + // cond: + // result: (XOR x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64XOR) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpNeqPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NeqPtr x y) + // cond: + // result: (NotEqual (CMP x y)) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64NotEqual) + v0 := b.NewValue0(v.Line, OpARM64CMP, TypeFlags) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + return true + } +} +func rewriteValueARM64_OpNilCheck(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (NilCheck ptr mem) + // cond: + // result: (LoweredNilCheck ptr mem) + for { + ptr := v.Args[0] + mem := v.Args[1] + v.reset(OpARM64LoweredNilCheck) + v.AddArg(ptr) + v.AddArg(mem) + return true + } +} +func rewriteValueARM64_OpNot(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Not x) + // cond: + // result: (XOR (MOVDconst [1]) x) + for { + x := v.Args[0] + v.reset(OpARM64XOR) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 1 + v.AddArg(v0) + v.AddArg(x) + return true + } +} +func rewriteValueARM64_OpOffPtr(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (OffPtr [off] ptr:(SP)) + // cond: + // result: (MOVDaddr [off] ptr) + for { + off := v.AuxInt + ptr := v.Args[0] + if ptr.Op != OpSP { + break + } + v.reset(OpARM64MOVDaddr) + v.AuxInt = off + v.AddArg(ptr) + return true + } + // match: (OffPtr [off] ptr) + // cond: + // result: (ADDconst [off] ptr) + for { + off := v.AuxInt + ptr := v.Args[0] + v.reset(OpARM64ADDconst) + v.AuxInt = off + v.AddArg(ptr) + return true + } +} +func rewriteValueARM64_OpOr16(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or16 x y) + // cond: + // result: (OR x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64OR) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpOr32(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or32 x y) + // cond: + // result: (OR x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64OR) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpOr64(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or64 x y) + // cond: + // result: (OR x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64OR) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpOr8(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Or8 x y) + // cond: + // result: (OR x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64OR) + v.AddArg(x) + v.AddArg(y) + return true + } +} +func rewriteValueARM64_OpOrB(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (OrB x y) + // cond: + // result: (OR x y) + for { + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64OR) + v.AddArg(x) + v.AddArg(y) + return true + } } -func rewriteValueARM64_OpMod16(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16Ux16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod16 x y) + // match: (Rsh16Ux16 x y) // cond: - // result: (MODW (SignExt16to32 x) (SignExt16to32 y)) + // result: (CSELULT (SRL (ZeroExt16to64 x) (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MODW) - v0 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32()) - v0.AddArg(x) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) v.AddArg(v0) - v1 := b.NewValue0(v.Line, OpSignExt16to32, config.fe.TypeInt32()) - v1.AddArg(y) - v.AddArg(v1) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpMod16u(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16Ux32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod16u x y) + // match: (Rsh16Ux32 x y) // cond: - // result: (UMODW (ZeroExt16to32 x) (ZeroExt16to32 y)) + // result: (CSELULT (SRL (ZeroExt16to64 x) (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64UMODW) - v0 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) - v0.AddArg(x) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) v.AddArg(v0) - v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) - v1.AddArg(y) - v.AddArg(v1) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpMod32(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16Ux64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod32 x y) + // match: (Rsh16Ux64 x (MOVDconst [c])) + // cond: uint64(c) < 16 + // result: (SRLconst (ZeroExt16to64 x) [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 16) { + break + } + v.reset(OpARM64SRLconst) + v0 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = c + return true + } + // match: (Rsh16Ux64 _ (MOVDconst [c])) + // cond: uint64(c) >= 16 + // result: (MOVDconst [0]) + for { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 16) { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 + return true + } + // match: (Rsh16Ux64 x y) // cond: - // result: (MODW x y) + // result: (CSELULT (SRL (ZeroExt16to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MODW) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v0.AddArg(y) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v3.AddArg(y) + v.AddArg(v3) return true } } -func rewriteValueARM64_OpMod32u(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16Ux8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod32u x y) + // match: (Rsh16Ux8 x y) // cond: - // result: (UMODW x y) + // result: (CSELULT (SRL (ZeroExt16to64 x) (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64UMODW) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpMod64(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16x16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod64 x y) + // match: (Rsh16x16 x y) // cond: - // result: (MOD x y) + // result: (SRA (SignExt16to64 x) (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MOD) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt16to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpMod64u(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16x32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod64u x y) + // match: (Rsh16x32 x y) // cond: - // result: (UMOD x y) + // result: (SRA (SignExt16to64 x) (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64UMOD) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt16to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpMod8(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16x64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod8 x y) + // match: (Rsh16x64 x (MOVDconst [c])) + // cond: uint64(c) < 16 + // result: (SRAconst (SignExt16to64 x) [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 16) { + break + } + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpSignExt16to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = c + return true + } + // match: (Rsh16x64 x (MOVDconst [c])) + // cond: uint64(c) >= 16 + // result: (SRAconst (SignExt16to64 x) [63]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 16) { + break + } + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpSignExt16to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = 63 + return true + } + // match: (Rsh16x64 x y) // cond: - // result: (MODW (SignExt8to32 x) (SignExt8to32 y)) + // result: (SRA (SignExt16to64 x) (CSELULT y (Const64 [63]) (CMPconst [64] y))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MODW) - v0 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32()) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt16to64, config.fe.TypeInt64()) v0.AddArg(x) v.AddArg(v0) - v1 := b.NewValue0(v.Line, OpSignExt8to32, config.fe.TypeInt32()) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) v1.AddArg(y) + v2 := b.NewValue0(v.Line, OpConst64, y.Type) + v2.AuxInt = 63 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v3.AddArg(y) + v1.AddArg(v3) v.AddArg(v1) return true } } -func rewriteValueARM64_OpMod8u(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh16x8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mod8u x y) + // match: (Rsh16x8 x y) // cond: - // result: (UMODW (ZeroExt8to32 x) (ZeroExt8to32 y)) + // result: (SRA (SignExt16to64 x) (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64UMODW) - v0 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt16to64, config.fe.TypeInt64()) v0.AddArg(x) v.AddArg(v0) - v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) - v1.AddArg(y) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) v.AddArg(v1) return true } } -func rewriteValueARM64_OpMul16(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32Ux16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mul16 x y) + // match: (Rsh32Ux16 x y) // cond: - // result: (MUL x y) + // result: (CSELULT (SRL (ZeroExt32to64 x) (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MUL) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpMul32(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32Ux32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mul32 x y) + // match: (Rsh32Ux32 x y) // cond: - // result: (MUL x y) + // result: (CSELULT (SRL (ZeroExt32to64 x) (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MUL) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpMul32F(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32Ux64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mul32F x y) + // match: (Rsh32Ux64 x (MOVDconst [c])) + // cond: uint64(c) < 32 + // result: (SRLconst (ZeroExt32to64 x) [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 32) { + break + } + v.reset(OpARM64SRLconst) + v0 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = c + return true + } + // match: (Rsh32Ux64 _ (MOVDconst [c])) + // cond: uint64(c) >= 32 + // result: (MOVDconst [0]) + for { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 32) { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 + return true + } + // match: (Rsh32Ux64 x y) // cond: - // result: (FMULS x y) + // result: (CSELULT (SRL (ZeroExt32to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64FMULS) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v0.AddArg(y) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v3.AddArg(y) + v.AddArg(v3) return true } } -func rewriteValueARM64_OpMul64(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32Ux8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mul64 x y) + // match: (Rsh32Ux8 x y) // cond: - // result: (MUL x y) + // result: (CSELULT (SRL (ZeroExt32to64 x) (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MUL) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpMul64F(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32x16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mul64F x y) + // match: (Rsh32x16 x y) // cond: - // result: (FMULD x y) + // result: (SRA (SignExt32to64 x) (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64FMULD) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt32to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpMul8(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32x32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Mul8 x y) + // match: (Rsh32x32 x y) // cond: - // result: (MUL x y) + // result: (SRA (SignExt32to64 x) (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64MUL) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt32to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpNeg16(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32x64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neg16 x) + // match: (Rsh32x64 x (MOVDconst [c])) + // cond: uint64(c) < 32 + // result: (SRAconst (SignExt32to64 x) [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 32) { + break + } + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpSignExt32to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = c + return true + } + // match: (Rsh32x64 x (MOVDconst [c])) + // cond: uint64(c) >= 32 + // result: (SRAconst (SignExt32to64 x) [63]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 32) { + break + } + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpSignExt32to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = 63 + return true + } + // match: (Rsh32x64 x y) // cond: - // result: (NEG x) + // result: (SRA (SignExt32to64 x) (CSELULT y (Const64 [63]) (CMPconst [64] y))) for { x := v.Args[0] - v.reset(OpARM64NEG) - v.AddArg(x) + y := v.Args[1] + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt32to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v1.AddArg(y) + v2 := b.NewValue0(v.Line, OpConst64, y.Type) + v2.AuxInt = 63 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v3.AddArg(y) + v1.AddArg(v3) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpNeg32(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh32x8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neg32 x) + // match: (Rsh32x8 x y) // cond: - // result: (NEG x) + // result: (SRA (SignExt32to64 x) (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v.Args[0] - v.reset(OpARM64NEG) - v.AddArg(x) + y := v.Args[1] + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt32to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpNeg32F(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64Ux16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neg32F x) + // match: (Rsh64Ux16 x y) // cond: - // result: (FNEGS x) + // result: (CSELULT (SRL x (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { + t := v.Type x := v.Args[0] - v.reset(OpARM64FNEGS) - v.AddArg(x) + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } } -func rewriteValueARM64_OpNeg64(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64Ux32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neg64 x) + // match: (Rsh64Ux32 x y) // cond: - // result: (NEG x) + // result: (CSELULT (SRL x (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { + t := v.Type x := v.Args[0] - v.reset(OpARM64NEG) - v.AddArg(x) + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } } -func rewriteValueARM64_OpNeg64F(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64Ux64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neg64F x) - // cond: - // result: (FNEGD x) + // match: (Rsh64Ux64 x (MOVDconst [c])) + // cond: uint64(c) < 64 + // result: (SRLconst x [c]) for { x := v.Args[0] - v.reset(OpARM64FNEGD) + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 64) { + break + } + v.reset(OpARM64SRLconst) v.AddArg(x) + v.AuxInt = c return true } -} -func rewriteValueARM64_OpNeg8(v *Value, config *Config) bool { - b := v.Block - _ = b - // match: (Neg8 x) + // match: (Rsh64Ux64 _ (MOVDconst [c])) + // cond: uint64(c) >= 64 + // result: (MOVDconst [0]) + for { + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 64) { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 + return true + } + // match: (Rsh64Ux64 x y) // cond: - // result: (NEG x) + // result: (CSELULT (SRL x y) (Const64 [0]) (CMPconst [64] y)) for { + t := v.Type x := v.Args[0] - v.reset(OpARM64NEG) - v.AddArg(x) + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v0.AddArg(x) + v0.AddArg(y) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpConst64, t) + v1.AuxInt = 0 + v.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v2.AuxInt = 64 + v2.AddArg(y) + v.AddArg(v2) return true } } -func rewriteValueARM64_OpNeq16(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64Ux8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neq16 x y) + // match: (Rsh64Ux8 x y) // cond: - // result: (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) + // result: (CSELULT (SRL x (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64CMPW, TypeFlags) - v1 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) - v1.AddArg(x) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v0.AddArg(x) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(y) v0.AddArg(v1) - v2 := b.NewValue0(v.Line, OpZeroExt16to32, config.fe.TypeUInt32()) - v2.AddArg(y) - v0.AddArg(v2) v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v.AddArg(v3) return true } } -func rewriteValueARM64_OpNeq32(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64x16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neq32 x y) + // match: (Rsh64x16 x y) // cond: - // result: (NotEqual (CMPW x y)) + // result: (SRA x (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64CMPW, TypeFlags) - v0.AddArg(x) - v0.AddArg(y) + v.reset(OpARM64SRA) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v1 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpConst64, y.Type) + v2.AuxInt = 63 + v0.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v0.AddArg(v3) v.AddArg(v0) return true } } -func rewriteValueARM64_OpNeq32F(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64x32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neq32F x y) + // match: (Rsh64x32 x y) // cond: - // result: (NotEqual (FCMPS x y)) + // result: (SRA x (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64FCMPS, TypeFlags) - v0.AddArg(x) - v0.AddArg(y) + v.reset(OpARM64SRA) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v1 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpConst64, y.Type) + v2.AuxInt = 63 + v0.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v0.AddArg(v3) v.AddArg(v0) return true } } -func rewriteValueARM64_OpNeq64(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64x64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neq64 x y) + // match: (Rsh64x64 x (MOVDconst [c])) + // cond: uint64(c) < 64 + // result: (SRAconst x [c]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 64) { + break + } + v.reset(OpARM64SRAconst) + v.AddArg(x) + v.AuxInt = c + return true + } + // match: (Rsh64x64 x (MOVDconst [c])) + // cond: uint64(c) >= 64 + // result: (SRAconst x [63]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 64) { + break + } + v.reset(OpARM64SRAconst) + v.AddArg(x) + v.AuxInt = 63 + return true + } + // match: (Rsh64x64 x y) // cond: - // result: (NotEqual (CMP x y)) + // result: (SRA x (CSELULT y (Const64 [63]) (CMPconst [64] y))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64CMP, TypeFlags) - v0.AddArg(x) + v.reset(OpARM64SRA) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) v0.AddArg(y) + v1 := b.NewValue0(v.Line, OpConst64, y.Type) + v1.AuxInt = 63 + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v2.AuxInt = 64 + v2.AddArg(y) + v0.AddArg(v2) v.AddArg(v0) return true } } -func rewriteValueARM64_OpNeq64F(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh64x8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neq64F x y) + // match: (Rsh64x8 x y) // cond: - // result: (NotEqual (FCMPD x y)) + // result: (SRA x (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64FCMPD, TypeFlags) - v0.AddArg(x) - v0.AddArg(y) + v.reset(OpARM64SRA) + v.AddArg(x) + v0 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(y) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpConst64, y.Type) + v2.AuxInt = 63 + v0.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v4 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v4.AddArg(y) + v3.AddArg(v4) + v0.AddArg(v3) v.AddArg(v0) return true } } -func rewriteValueARM64_OpNeq8(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8Ux16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Neq8 x y) + // match: (Rsh8Ux16 x y) // cond: - // result: (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) + // result: (CSELULT (SRL (ZeroExt8to64 x) (ZeroExt16to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt16to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64CMPW, TypeFlags) - v1 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) v1.AddArg(x) v0.AddArg(v1) - v2 := b.NewValue0(v.Line, OpZeroExt8to32, config.fe.TypeUInt32()) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) v2.AddArg(y) v0.AddArg(v2) v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpNeqB(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8Ux32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (NeqB x y) + // match: (Rsh8Ux32 x y) // cond: - // result: (XOR x y) + // result: (CSELULT (SRL (ZeroExt8to64 x) (ZeroExt32to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt32to64 y))) for { + t := v.Type x := v.Args[0] y := v.Args[1] - v.reset(OpARM64XOR) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpNeqPtr(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8Ux64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (NeqPtr x y) - // cond: - // result: (NotEqual (CMP x y)) + // match: (Rsh8Ux64 x (MOVDconst [c])) + // cond: uint64(c) < 8 + // result: (SRLconst (ZeroExt8to64 x) [c]) for { x := v.Args[0] - y := v.Args[1] - v.reset(OpARM64NotEqual) - v0 := b.NewValue0(v.Line, OpARM64CMP, TypeFlags) + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 8) { + break + } + v.reset(OpARM64SRLconst) + v0 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) v0.AddArg(x) - v0.AddArg(y) v.AddArg(v0) + v.AuxInt = c return true } -} -func rewriteValueARM64_OpNilCheck(v *Value, config *Config) bool { - b := v.Block - _ = b - // match: (NilCheck ptr mem) - // cond: - // result: (LoweredNilCheck ptr mem) + // match: (Rsh8Ux64 _ (MOVDconst [c])) + // cond: uint64(c) >= 8 + // result: (MOVDconst [0]) for { - ptr := v.Args[0] - mem := v.Args[1] - v.reset(OpARM64LoweredNilCheck) - v.AddArg(ptr) - v.AddArg(mem) + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 8) { + break + } + v.reset(OpARM64MOVDconst) + v.AuxInt = 0 return true } -} -func rewriteValueARM64_OpNot(v *Value, config *Config) bool { - b := v.Block - _ = b - // match: (Not x) + // match: (Rsh8Ux64 x y) // cond: - // result: (XORconst [1] x) + // result: (CSELULT (SRL (ZeroExt8to64 x) y) (Const64 [0]) (CMPconst [64] y)) for { + t := v.Type x := v.Args[0] - v.reset(OpARM64XORconst) - v.AuxInt = 1 - v.AddArg(x) + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v0.AddArg(y) + v.AddArg(v0) + v2 := b.NewValue0(v.Line, OpConst64, t) + v2.AuxInt = 0 + v.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v3.AddArg(y) + v.AddArg(v3) return true } } -func rewriteValueARM64_OpOffPtr(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8Ux8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (OffPtr [off] ptr:(SP)) - // cond: - // result: (MOVDaddr [off] ptr) - for { - off := v.AuxInt - ptr := v.Args[0] - if ptr.Op != OpSP { - break - } - v.reset(OpARM64MOVDaddr) - v.AuxInt = off - v.AddArg(ptr) - return true - } - // match: (OffPtr [off] ptr) + // match: (Rsh8Ux8 x y) // cond: - // result: (ADDconst [off] ptr) + // result: (CSELULT (SRL (ZeroExt8to64 x) (ZeroExt8to64 y)) (Const64 [0]) (CMPconst [64] (ZeroExt8to64 y))) for { - off := v.AuxInt - ptr := v.Args[0] - v.reset(OpARM64ADDconst) - v.AuxInt = off - v.AddArg(ptr) + t := v.Type + x := v.Args[0] + y := v.Args[1] + v.reset(OpARM64CSELULT) + v0 := b.NewValue0(v.Line, OpARM64SRL, t) + v1 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v1.AddArg(x) + v0.AddArg(v1) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v0.AddArg(v2) + v.AddArg(v0) + v3 := b.NewValue0(v.Line, OpConst64, t) + v3.AuxInt = 0 + v.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v.AddArg(v4) return true } } -func rewriteValueARM64_OpOr16(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8x16(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Or16 x y) + // match: (Rsh8x16 x y) // cond: - // result: (OR x y) + // result: (SRA (SignExt8to64 x) (CSELULT (ZeroExt16to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt16to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64OR) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt8to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt16to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpOr32(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8x32(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Or32 x y) + // match: (Rsh8x32 x y) // cond: - // result: (OR x y) + // result: (SRA (SignExt8to64 x) (CSELULT (ZeroExt32to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt32to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64OR) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt8to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt32to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpOr64(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8x64(v *Value, config *Config) bool { b := v.Block _ = b - // match: (Or64 x y) - // cond: - // result: (OR x y) + // match: (Rsh8x64 x (MOVDconst [c])) + // cond: uint64(c) < 8 + // result: (SRAconst (SignExt8to64 x) [c]) for { x := v.Args[0] - y := v.Args[1] - v.reset(OpARM64OR) - v.AddArg(x) - v.AddArg(y) + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) < 8) { + break + } + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpSignExt8to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = c return true } -} -func rewriteValueARM64_OpOr8(v *Value, config *Config) bool { - b := v.Block - _ = b - // match: (Or8 x y) + // match: (Rsh8x64 x (MOVDconst [c])) + // cond: uint64(c) >= 8 + // result: (SRAconst (SignExt8to64 x) [63]) + for { + x := v.Args[0] + v_1 := v.Args[1] + if v_1.Op != OpARM64MOVDconst { + break + } + c := v_1.AuxInt + if !(uint64(c) >= 8) { + break + } + v.reset(OpARM64SRAconst) + v0 := b.NewValue0(v.Line, OpSignExt8to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v.AuxInt = 63 + return true + } + // match: (Rsh8x64 x y) // cond: - // result: (OR x y) + // result: (SRA (SignExt8to64 x) (CSELULT y (Const64 [63]) (CMPconst [64] y))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64OR) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt8to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v1.AddArg(y) + v2 := b.NewValue0(v.Line, OpConst64, y.Type) + v2.AuxInt = 63 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v3.AuxInt = 64 + v3.AddArg(y) + v1.AddArg(v3) + v.AddArg(v1) return true } } -func rewriteValueARM64_OpOrB(v *Value, config *Config) bool { +func rewriteValueARM64_OpRsh8x8(v *Value, config *Config) bool { b := v.Block _ = b - // match: (OrB x y) + // match: (Rsh8x8 x y) // cond: - // result: (OR x y) + // result: (SRA (SignExt8to64 x) (CSELULT (ZeroExt8to64 y) (Const64 [63]) (CMPconst [64] (ZeroExt8to64 y)))) for { x := v.Args[0] y := v.Args[1] - v.reset(OpARM64OR) - v.AddArg(x) - v.AddArg(y) + v.reset(OpARM64SRA) + v0 := b.NewValue0(v.Line, OpSignExt8to64, config.fe.TypeInt64()) + v0.AddArg(x) + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64CSELULT, y.Type) + v2 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v2.AddArg(y) + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpConst64, y.Type) + v3.AuxInt = 63 + v1.AddArg(v3) + v4 := b.NewValue0(v.Line, OpARM64CMPconst, TypeFlags) + v4.AuxInt = 64 + v5 := b.NewValue0(v.Line, OpZeroExt8to64, config.fe.TypeUInt64()) + v5.AddArg(y) + v4.AddArg(v5) + v1.AddArg(v4) + v.AddArg(v1) return true } } @@ -3714,6 +6404,19 @@ func rewriteValueARM64_OpSignExt8to64(v *Value, config *Config) bool { return true } } +func rewriteValueARM64_OpSqrt(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Sqrt x) + // cond: + // result: (FSQRTD x) + for { + x := v.Args[0] + v.reset(OpARM64FSQRTD) + v.AddArg(x) + return true + } +} func rewriteValueARM64_OpStaticCall(v *Value, config *Config) bool { b := v.Block _ = b @@ -4093,6 +6796,439 @@ func rewriteValueARM64_OpXor8(v *Value, config *Config) bool { return true } } +func rewriteValueARM64_OpZero(v *Value, config *Config) bool { + b := v.Block + _ = b + // match: (Zero [s] _ mem) + // cond: SizeAndAlign(s).Size() == 0 + // result: mem + for { + s := v.AuxInt + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 0) { + break + } + v.reset(OpCopy) + v.Type = mem.Type + v.AddArg(mem) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 1 + // result: (MOVBstore ptr (MOVDconst [0]) mem) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 1) { + break + } + v.reset(OpARM64MOVBstore) + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore ptr (MOVDconst [0]) mem) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 2 + // result: (MOVBstore [1] ptr (MOVDconst [0]) (MOVBstore ptr (MOVDconst [0]) mem)) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 2) { + break + } + v.reset(OpARM64MOVBstore) + v.AuxInt = 1 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 + // result: (MOVWstore ptr (MOVDconst [0]) mem) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0) { + break + } + v.reset(OpARM64MOVWstore) + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem)) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AuxInt = 2 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 4 + // result: (MOVBstore [3] ptr (MOVDconst [0]) (MOVBstore [2] ptr (MOVDconst [0]) (MOVBstore [1] ptr (MOVDconst [0]) (MOVBstore ptr (MOVDconst [0]) mem)))) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 4) { + break + } + v.reset(OpARM64MOVBstore) + v.AuxInt = 3 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v1.AuxInt = 2 + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v3.AuxInt = 1 + v3.AddArg(ptr) + v4 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v4.AuxInt = 0 + v3.AddArg(v4) + v5 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v5.AddArg(ptr) + v6 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v6.AuxInt = 0 + v5.AddArg(v6) + v5.AddArg(mem) + v3.AddArg(v5) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 + // result: (MOVDstore ptr (MOVDconst [0]) mem) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0) { + break + } + v.reset(OpARM64MOVDstore) + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v.AddArg(mem) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 + // result: (MOVWstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem)) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0) { + break + } + v.reset(OpARM64MOVWstore) + v.AuxInt = 4 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVWstore, TypeMem) + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore [6] ptr (MOVDconst [0]) (MOVHstore [4] ptr (MOVDconst [0]) (MOVHstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem)))) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AuxInt = 6 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v1.AuxInt = 4 + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v3.AuxInt = 2 + v3.AddArg(ptr) + v4 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v4.AuxInt = 0 + v3.AddArg(v4) + v5 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v5.AddArg(ptr) + v6 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v6.AuxInt = 0 + v5.AddArg(v6) + v5.AddArg(mem) + v3.AddArg(v5) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 3 + // result: (MOVBstore [2] ptr (MOVDconst [0]) (MOVBstore [1] ptr (MOVDconst [0]) (MOVBstore ptr (MOVDconst [0]) mem))) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 3) { + break + } + v.reset(OpARM64MOVBstore) + v.AuxInt = 2 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v1.AuxInt = 1 + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVBstore, TypeMem) + v3.AddArg(ptr) + v4 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v4.AuxInt = 0 + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 + // result: (MOVHstore [4] ptr (MOVDconst [0]) (MOVHstore [2] ptr (MOVDconst [0]) (MOVHstore ptr (MOVDconst [0]) mem))) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0) { + break + } + v.reset(OpARM64MOVHstore) + v.AuxInt = 4 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v1.AuxInt = 2 + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVHstore, TypeMem) + v3.AddArg(ptr) + v4 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v4.AuxInt = 0 + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 + // result: (MOVWstore [8] ptr (MOVDconst [0]) (MOVWstore [4] ptr (MOVDconst [0]) (MOVWstore ptr (MOVDconst [0]) mem))) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0) { + break + } + v.reset(OpARM64MOVWstore) + v.AuxInt = 8 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVWstore, TypeMem) + v1.AuxInt = 4 + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVWstore, TypeMem) + v3.AddArg(ptr) + v4 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v4.AuxInt = 0 + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 + // result: (MOVDstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem)) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0) { + break + } + v.reset(OpARM64MOVDstore) + v.AuxInt = 8 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVDstore, TypeMem) + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v1.AddArg(mem) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 + // result: (MOVDstore [16] ptr (MOVDconst [0]) (MOVDstore [8] ptr (MOVDconst [0]) (MOVDstore ptr (MOVDconst [0]) mem))) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0) { + break + } + v.reset(OpARM64MOVDstore) + v.AuxInt = 16 + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v0.AuxInt = 0 + v.AddArg(v0) + v1 := b.NewValue0(v.Line, OpARM64MOVDstore, TypeMem) + v1.AuxInt = 8 + v1.AddArg(ptr) + v2 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v2.AuxInt = 0 + v1.AddArg(v2) + v3 := b.NewValue0(v.Line, OpARM64MOVDstore, TypeMem) + v3.AddArg(ptr) + v4 := b.NewValue0(v.Line, OpARM64MOVDconst, config.fe.TypeUInt64()) + v4.AuxInt = 0 + v3.AddArg(v4) + v3.AddArg(mem) + v1.AddArg(v3) + v.AddArg(v1) + return true + } + // match: (Zero [s] ptr mem) + // cond: SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice + // result: (DUFFZERO [4 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !(SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice) { + break + } + v.reset(OpARM64DUFFZERO) + v.AuxInt = 4 * (128 - int64(SizeAndAlign(s).Size()/8)) + v.AddArg(ptr) + v.AddArg(mem) + return true + } + // match: (Zero [s] ptr mem) + // cond: (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0 + // result: (LoweredZero [SizeAndAlign(s).Align()] ptr (ADDconst [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)] ptr) mem) + for { + s := v.AuxInt + ptr := v.Args[0] + mem := v.Args[1] + if !((SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0) { + break + } + v.reset(OpARM64LoweredZero) + v.AuxInt = SizeAndAlign(s).Align() + v.AddArg(ptr) + v0 := b.NewValue0(v.Line, OpARM64ADDconst, ptr.Type) + v0.AuxInt = SizeAndAlign(s).Size() - moveSize(SizeAndAlign(s).Align(), config) + v0.AddArg(ptr) + v.AddArg(v0) + v.AddArg(mem) + return true + } + return false +} func rewriteValueARM64_OpZeroExt16to32(v *Value, config *Config) bool { b := v.Block _ = b diff --git a/src/cmd/compile/internal/ssa/schedule.go b/src/cmd/compile/internal/ssa/schedule.go index 73ef72e53b..86f1461c42 100644 --- a/src/cmd/compile/internal/ssa/schedule.go +++ b/src/cmd/compile/internal/ssa/schedule.go @@ -84,7 +84,7 @@ func schedule(f *Func) { // Compute score. Larger numbers are scheduled closer to the end of the block. for _, v := range b.Values { switch { - case v.Op == OpAMD64LoweredGetClosurePtr || v.Op == OpPPC64LoweredGetClosurePtr || v.Op == OpARMLoweredGetClosurePtr || v.Op == Op386LoweredGetClosurePtr: + case v.Op == OpAMD64LoweredGetClosurePtr || v.Op == OpPPC64LoweredGetClosurePtr || v.Op == OpARMLoweredGetClosurePtr || v.Op == OpARM64LoweredGetClosurePtr || v.Op == Op386LoweredGetClosurePtr: // We also score GetLoweredClosurePtr as early as possible to ensure that the // context register is not stomped. GetLoweredClosurePtr should only appear // in the entry block where there are no phi functions, so there is no