From: Shenghou Ma <minux@golang.org>
Date: Sat, 4 Apr 2015 05:47:55 +0000 (-0400)
Subject: cmd/asm/internal/asm: parse arm64 register pairs for LDP/STP
X-Git-Tag: go1.5beta1~1262
X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=a175fa3bc3a69b4090eb594af9203d0f0fb9cf44;p=gostls13.git

cmd/asm/internal/asm: parse arm64 register pairs for LDP/STP

Add test, and while we're at here, also add a test for ARM.

Fixes #10343.

Change-Id: Ic914df8233d4f1f495e2cc0743fbd37b7671bc91
Signed-off-by: Shenghou Ma <minux@golang.org>
Reviewed-on: https://go-review.googlesource.com/8472
Reviewed-by: Aram Hăvărneanu <aram@mgk.ro>
Reviewed-by: Rob Pike <r@golang.org>
---

diff --git a/src/cmd/asm/internal/asm/operand_test.go b/src/cmd/asm/internal/asm/operand_test.go
index 1b10a3ad10..b9154a91e9 100644
--- a/src/cmd/asm/internal/asm/operand_test.go
+++ b/src/cmd/asm/internal/asm/operand_test.go
@@ -287,6 +287,7 @@ var armOperandTests = []operandTest{
 	{"retlo+12(FP)", "retlo+12(FP)"},
 	{"runtime·_sfloat2(SB)", "runtime._sfloat2(SB)"},
 	{"·AddUint32(SB)", "\"\".AddUint32(SB)"},
+	{"(R1, R3)", "(R1, R3)"},
 }
 
 var ppc64OperandTests = []operandTest{
@@ -424,4 +425,5 @@ var arm64OperandTests = []operandTest{
 	{"$runtime·badsystemstack(SB)", "$runtime.badsystemstack(SB)"},
 	{"ZR", "ZR"},
 	{"(ZR)", "(ZR)"},
+	{"(R29, RSP)", "(R29, RSP)"},
 }
diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go
index 81d7cccd0e..6b67451d5f 100644
--- a/src/cmd/asm/internal/asm/parse.go
+++ b/src/cmd/asm/internal/asm/parse.go
@@ -461,7 +461,7 @@ func (p *Parser) register(name string, prefix rune) (r1, r2 int16, scale int8, o
 		char := p.arch.Thechar
 		switch p.next().ScanToken {
 		case ',':
-			if char != '5' {
+			if char != '5' && char != '7' {
 				p.errorf("illegal register pair syntax")
 				return
 			}
@@ -629,15 +629,17 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
 	a.Reg = r1
 	if r2 != 0 {
 		// TODO: Consistency in the encoding would be nice here.
-		if p.arch.Thechar == '5' {
-			// Special form for ARM: destination register pair (R1, R2).
+		if p.arch.Thechar == '5' || p.arch.Thechar == '7' {
+			// Special form
+			// ARM: destination register pair (R1, R2).
+			// ARM64: register pair (R1, R2) for LDP/STP.
 			if prefix != 0 || scale != 0 {
 				p.errorf("illegal address mode for register pair")
 				return
 			}
 			a.Type = obj.TYPE_REGREG
 			a.Offset = int64(r2)
-			// Nothing may follow; this is always a pure destination.
+			// Nothing may follow
 			return
 		}
 		if p.arch.Thechar == '9' {