From: Cherry Zhang <cherryyz@google.com>
Date: Fri, 12 Mar 2021 23:45:52 +0000 (-0500)
Subject: cmd/compile: remove ARMv5 special case in register allocator
X-Git-Tag: go1.17beta1~1129
X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=c4190fc34dbfe8c7859a91b07ed31a33633d08df;p=gostls13.git

cmd/compile: remove ARMv5 special case in register allocator

The register allocator has a special case that doesn't allocate
LR on ARMv5. This was necessary when softfloat expansion was done
by the assembler. Now softfloat calls are inserted by SSA, so it
works as normal. Remove this special case.

Change-Id: I5502f07597f4d4b675dc16b6b0d7cb47e1e8974b
Reviewed-on: https://go-review.googlesource.com/c/go/+/301792
Trust: Cherry Zhang <cherryyz@google.com>
Reviewed-by: David Chase <drchase@google.com>
---

diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go
index 15f6412a85..c104a36888 100644
--- a/src/cmd/compile/internal/ssa/regalloc.go
+++ b/src/cmd/compile/internal/ssa/regalloc.go
@@ -605,12 +605,6 @@ func (s *regAllocState) init(f *Func) {
 			// Leaf functions don't save/restore the link register.
 			s.allocatable &^= 1 << uint(s.f.Config.LinkReg)
 		}
-		if s.f.Config.arch == "arm" && objabi.GOARM == 5 {
-			// On ARMv5 we insert softfloat calls at each FP instruction.
-			// This clobbers LR almost everywhere. Disable allocating LR
-			// on ARMv5.
-			s.allocatable &^= 1 << uint(s.f.Config.LinkReg)
-		}
 	}
 	if s.f.Config.ctxt.Flag_dynlink {
 		switch s.f.Config.arch {