From: Joel Sing Date: Wed, 18 Sep 2019 14:59:26 +0000 (+1000) Subject: cmd/internal/obj/riscv: implement RV64I integer computational instructions X-Git-Tag: go1.14beta1~1006 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=e29d276d55bc0743a0fb66ea4a4967f937153567;p=gostls13.git cmd/internal/obj/riscv: implement RV64I integer computational instructions Add support for assembling RV64I integer computational instructions. Based on the riscv-go port. Updates #27532 Integer Computational Instructions (RV64I) Change-Id: I1a082b3901c997da309d737d081f57ea2821bc62 Reviewed-on: https://go-review.googlesource.com/c/go/+/196838 Reviewed-by: Cherry Zhang Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot --- diff --git a/src/cmd/asm/internal/asm/testdata/riscvenc.s b/src/cmd/asm/internal/asm/testdata/riscvenc.s index 1902138504..8ee7f18a16 100644 --- a/src/cmd/asm/internal/asm/testdata/riscvenc.s +++ b/src/cmd/asm/internal/asm/testdata/riscvenc.s @@ -95,6 +95,17 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 SB $0, X5, X6 // 23005300 SB $4, X5, X6 // 23025300 + // 5.2: Integer Computational Instructions (RV64I) + ADDIW $1, X5, X6 // 1b831200 + SLLIW $1, X5, X6 // 1b931200 + SRLIW $1, X5, X6 // 1bd31200 + SRAIW $1, X5, X6 // 1bd31240 + ADDW X5, X6, X7 // bb035300 + SLLW X5, X6, X7 // bb135300 + SRLW X5, X6, X7 // bb535300 + SUBW X5, X6, X7 // bb035340 + SRAW X5, X6, X7 // bb535340 + // 5.3: Load and Store Instructions (RV64I) LD $0, X5, X6 // 03b30200 LD $4, X5, X6 // 03b34200 diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index 1182053191..46188c1e30 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -401,6 +401,17 @@ var encodingForAs = [ALAST & obj.AMask]encoding{ ASH & obj.AMask: sIEncoding, ASB & obj.AMask: sIEncoding, + // 5.2: Integer Computational Instructions (RV64I) + AADDIW & obj.AMask: iIEncoding, + ASLLIW & obj.AMask: iIEncoding, + ASRLIW & obj.AMask: iIEncoding, + ASRAIW & obj.AMask: iIEncoding, + AADDW & obj.AMask: rIIIEncoding, + ASLLW & obj.AMask: rIIIEncoding, + ASRLW & obj.AMask: rIIIEncoding, + ASUBW & obj.AMask: rIIIEncoding, + ASRAW & obj.AMask: rIIIEncoding, + // 5.3: Load and Store Instructions (RV64I) ALD & obj.AMask: iIEncoding, ASD & obj.AMask: sIEncoding,