From: Meng Zhuo Date: Tue, 16 Mar 2021 10:51:41 +0000 (+0800) Subject: cmd/asm: add rotr/drotr for mips64 X-Git-Tag: go1.17beta1~1102 X-Git-Url: http://www.git.cypherpunks.su/?a=commitdiff_plain;h=e31e84010e0989e1df4bd2c55d529497119bb345;p=gostls13.git cmd/asm: add rotr/drotr for mips64 This CL encodes: ROTR rd, rt, sa ROTRV rd, rt, rs => ROTR (SCON|REG), (REG,)? REG DROTR rd, rt, sa DROTR32 rd, rt, sa DROTRV rd, rt, rs => ROTRV (SCON|REG), (REG,)? REG Note: ROTRV will handle const over 32 Ref: The MIPS64® Instruction Set Reference Manual Revision 6.05 Change-Id: Ibe69f999b83eb43843d088cf1ac5a13c995269a5 Reviewed-on: https://go-review.googlesource.com/c/go/+/280114 Trust: Meng Zhuo Run-TryBot: Meng Zhuo TryBot-Result: Go Bot Reviewed-by: Cherry Zhang --- diff --git a/src/cmd/asm/internal/asm/testdata/mips64.s b/src/cmd/asm/internal/asm/testdata/mips64.s index 21ab82f319..99044d89f7 100644 --- a/src/cmd/asm/internal/asm/testdata/mips64.s +++ b/src/cmd/asm/internal/asm/testdata/mips64.s @@ -407,6 +407,8 @@ label4: SRLV R27, R6, R17 // 03668816 SRA R11, R19, R20 // 0173a007 SRAV R20, R19, R19 // 02939817 + ROTR R19, R18, R20 // 0272a046 + ROTRV R9, R13, R16 // 012d8056 // LSHW rreg ',' rreg // { @@ -418,6 +420,8 @@ label4: SRLV R27, R6 // 03663016 SRA R11, R19 // 01739807 SRAV R20, R19 // 02939817 + ROTR R20, R19 // 02939846 + ROTRV R16, R9 // 02094856 // LSHW imm ',' sreg ',' rreg // { @@ -429,6 +433,8 @@ label4: SRLV $31, R6, R17 // 00068ffa SRA $8, R8, R19 // 00089a03 SRAV $19, R8, R7 // 00083cfb + ROTR $12, R8, R3 // 00281b02 + ROTRV $8, R22, R22 // 0036b23a // LSHW imm ',' rreg // { @@ -440,6 +446,8 @@ label4: SRLV $31, R17 // 00118ffa SRA $3, R12 // 000c60c3 SRAV $12, R3 // 00031b3b + ROTR $12, R8 // 00284302 + ROTRV $63, R22 // 0036b7fe // LAND/LXOR/LNOR/LOR rreg ',' rreg diff --git a/src/cmd/internal/obj/mips/a.out.go b/src/cmd/internal/obj/mips/a.out.go index ddd048a17f..c6ce53a8da 100644 --- a/src/cmd/internal/obj/mips/a.out.go +++ b/src/cmd/internal/obj/mips/a.out.go @@ -390,6 +390,8 @@ const ( AREM AREMU ARFE + AROTR + AROTRV ASC ASCV ASGT diff --git a/src/cmd/internal/obj/mips/anames.go b/src/cmd/internal/obj/mips/anames.go index 2a44e4ca70..ca2ad5ae26 100644 --- a/src/cmd/internal/obj/mips/anames.go +++ b/src/cmd/internal/obj/mips/anames.go @@ -78,6 +78,8 @@ var Anames = []string{ "REM", "REMU", "RFE", + "ROTR", + "ROTRV", "SC", "SCV", "SGT", diff --git a/src/cmd/internal/obj/mips/asm0.go b/src/cmd/internal/obj/mips/asm0.go index fd29f9fa21..e475ffdc14 100644 --- a/src/cmd/internal/obj/mips/asm0.go +++ b/src/cmd/internal/obj/mips/asm0.go @@ -1022,10 +1022,12 @@ func buildop(ctxt *obj.Link) { case ASLL: opset(ASRL, r0) opset(ASRA, r0) + opset(AROTR, r0) case ASLLV: opset(ASRAV, r0) opset(ASRLV, r0) + opset(AROTRV, r0) case ASUB: opset(ASUBU, r0) @@ -1732,12 +1734,16 @@ func (c *ctxt0) oprrr(a obj.As) uint32 { return OP(0, 6) case ASRA: return OP(0, 7) + case AROTR: + return OP(8, 6) case ASLLV: return OP(2, 4) case ASRLV: return OP(2, 6) case ASRAV: return OP(2, 7) + case AROTRV: + return OP(10, 6) case AADDV: return OP(5, 4) case AADDVU: @@ -1916,6 +1922,8 @@ func (c *ctxt0) opirr(a obj.As) uint32 { return OP(0, 2) case ASRA: return OP(0, 3) + case AROTR: + return OP(0, 2) | 1<<21 case AADDV: return SP(3, 0) case AADDVU: @@ -2028,12 +2036,16 @@ func (c *ctxt0) opirr(a obj.As) uint32 { return OP(7, 2) case ASRAV: return OP(7, 3) + case AROTRV: + return OP(7, 2) | 1<<21 case -ASLLV: return OP(7, 4) case -ASRLV: return OP(7, 6) case -ASRAV: return OP(7, 7) + case -AROTRV: + return OP(7, 6) | 1<<21 case ATEQ: return OP(6, 4) @@ -2061,7 +2073,8 @@ func vshift(a obj.As) bool { switch a { case ASLLV, ASRLV, - ASRAV: + ASRAV, + AROTRV: return true } return false