From 1b541502c2aaaf3be073e79a9ea211a147c2e006 Mon Sep 17 00:00:00 2001 From: "Paul E. Murphy" Date: Tue, 14 Nov 2023 14:58:49 -0600 Subject: [PATCH] cmd/internal/obj/ppc64: rename and remove aliased optab classifiers Rename C_LCON, C_SCON, C_ADDCON, C_ANDCON into their aliased names and remove them. Change-Id: I8f67cc973f8059e65b81669d91a44500fc136b0a Reviewed-on: https://go-review.googlesource.com/c/go/+/563097 Run-TryBot: Paul Murphy Reviewed-by: Lynn Boger Reviewed-by: Than McIntosh Reviewed-by: David Chase TryBot-Result: Gopher Robot --- src/cmd/internal/obj/ppc64/a.out.go | 6 - src/cmd/internal/obj/ppc64/asm9.go | 248 ++++++++++++++-------------- 2 files changed, 124 insertions(+), 130 deletions(-) diff --git a/src/cmd/internal/obj/ppc64/a.out.go b/src/cmd/internal/obj/ppc64/a.out.go index c18556f1f3..ab1b4eb19f 100644 --- a/src/cmd/internal/obj/ppc64/a.out.go +++ b/src/cmd/internal/obj/ppc64/a.out.go @@ -449,12 +449,6 @@ const ( C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */ C_NCLASS /* must be the last */ - - /* Aliased names which should be cleaned up, or integrated. */ - C_SCON = C_U15CON - C_ADDCON = C_S16CON - C_ANDCON = C_U16CON - C_LCON = C_32CON ) const ( diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go index 2455d6ad2e..375fc0ed29 100644 --- a/src/cmd/internal/obj/ppc64/asm9.go +++ b/src/cmd/internal/obj/ppc64/asm9.go @@ -110,60 +110,60 @@ var optab []Optab var optabBase = []Optab{ {as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0}, - {as: obj.ATEXT, a1: C_LOREG, a3: C_LCON, a6: C_TEXTSIZE, type_: 0, size: 0}, + {as: obj.ATEXT, a1: C_LOREG, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0}, {as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0}, - {as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE, type_: 0, size: 0}, + {as: obj.ATEXT, a1: C_ADDR, a3: C_32CON, a6: C_TEXTSIZE, type_: 0, size: 0}, /* move register */ {as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4}, {as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4}, - {as: AADD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, - {as: AADD, a1: C_SCON, a6: C_REG, type_: 4, size: 4}, - {as: AADD, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, - {as: AADD, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4}, - {as: AADD, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 22, size: 8}, - {as: AADD, a1: C_ANDCON, a6: C_REG, type_: 22, size: 8}, - {as: AADDIS, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 20, size: 4}, - {as: AADDIS, a1: C_ADDCON, a6: C_REG, type_: 20, size: 4}, + {as: AADD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, + {as: AADD, a1: C_U15CON, a6: C_REG, type_: 4, size: 4}, + {as: AADD, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, + {as: AADD, a1: C_S16CON, a6: C_REG, type_: 4, size: 4}, + {as: AADD, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 22, size: 8}, + {as: AADD, a1: C_U16CON, a6: C_REG, type_: 22, size: 8}, + {as: AADDIS, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 20, size: 4}, + {as: AADDIS, a1: C_S16CON, a6: C_REG, type_: 20, size: 4}, {as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4}, {as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4}, - {as: AADDC, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, - {as: AADDC, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4}, - {as: AADDC, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, - {as: AADDC, a1: C_LCON, a6: C_REG, type_: 22, size: 12}, + {as: AADDC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, + {as: AADDC, a1: C_S16CON, a6: C_REG, type_: 4, size: 4}, + {as: AADDC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, + {as: AADDC, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, {as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, /* logical, no literal */ {as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4}, {as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, {as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4}, - {as: AANDCC, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4}, - {as: AANDCC, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, - {as: AANDCC, a1: C_ADDCON, a6: C_REG, type_: 23, size: 8}, - {as: AANDCC, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 23, size: 8}, - {as: AANDCC, a1: C_LCON, a6: C_REG, type_: 23, size: 12}, - {as: AANDCC, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 23, size: 12}, - {as: AANDISCC, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4}, - {as: AANDISCC, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, + {as: AANDCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4}, + {as: AANDCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, + {as: AANDCC, a1: C_S16CON, a6: C_REG, type_: 23, size: 8}, + {as: AANDCC, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8}, + {as: AANDCC, a1: C_32CON, a6: C_REG, type_: 23, size: 12}, + {as: AANDCC, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12}, + {as: AANDISCC, a1: C_U16CON, a6: C_REG, type_: 58, size: 4}, + {as: AANDISCC, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, {as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4}, {as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4}, - {as: AMULLW, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, - {as: AMULLW, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4}, - {as: AMULLW, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, - {as: AMULLW, a1: C_ANDCON, a6: C_REG, type_: 4, size: 4}, - {as: AMULLW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, - {as: AMULLW, a1: C_LCON, a6: C_REG, type_: 22, size: 12}, + {as: AMULLW, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, + {as: AMULLW, a1: C_S16CON, a6: C_REG, type_: 4, size: 4}, + {as: AMULLW, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 4, size: 4}, + {as: AMULLW, a1: C_U16CON, a6: C_REG, type_: 4, size: 4}, + {as: AMULLW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, + {as: AMULLW, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, {as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4}, {as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4}, - {as: ASUBC, a1: C_REG, a3: C_ADDCON, a6: C_REG, type_: 27, size: 4}, - {as: ASUBC, a1: C_REG, a3: C_LCON, a6: C_REG, type_: 28, size: 12}, + {as: ASUBC, a1: C_REG, a3: C_S16CON, a6: C_REG, type_: 27, size: 4}, + {as: ASUBC, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 28, size: 12}, {as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, /* logical, literal not cc (or/xor) */ {as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4}, - {as: AOR, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4}, - {as: AOR, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, - {as: AOR, a1: C_ADDCON, a6: C_REG, type_: 23, size: 8}, - {as: AOR, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 23, size: 8}, - {as: AOR, a1: C_LCON, a6: C_REG, type_: 23, size: 12}, - {as: AOR, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 23, size: 12}, - {as: AORIS, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4}, - {as: AORIS, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, + {as: AOR, a1: C_U16CON, a6: C_REG, type_: 58, size: 4}, + {as: AOR, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, + {as: AOR, a1: C_S16CON, a6: C_REG, type_: 23, size: 8}, + {as: AOR, a1: C_S16CON, a2: C_REG, a6: C_REG, type_: 23, size: 8}, + {as: AOR, a1: C_32CON, a6: C_REG, type_: 23, size: 12}, + {as: AOR, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 23, size: 12}, + {as: AORIS, a1: C_U16CON, a6: C_REG, type_: 58, size: 4}, + {as: AORIS, a1: C_U16CON, a2: C_REG, a6: C_REG, type_: 58, size: 4}, {as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4}, /* op r1[,r2],r3 */ {as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4}, {as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4}, /* op r2[,r1],r3 */ @@ -172,33 +172,33 @@ var optabBase = []Optab{ {as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, {as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4}, {as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, - {as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 25, size: 4}, - {as: ASLD, a1: C_SCON, a6: C_REG, type_: 25, size: 4}, - {as: AEXTSWSLI, a1: C_SCON, a6: C_REG, type_: 25, size: 4}, - {as: AEXTSWSLI, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 25, size: 4}, - {as: ASLW, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 57, size: 4}, - {as: ASLW, a1: C_SCON, a6: C_REG, type_: 57, size: 4}, + {as: ASLD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4}, + {as: ASLD, a1: C_U15CON, a6: C_REG, type_: 25, size: 4}, + {as: AEXTSWSLI, a1: C_U15CON, a6: C_REG, type_: 25, size: 4}, + {as: AEXTSWSLI, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 25, size: 4}, + {as: ASLW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 57, size: 4}, + {as: ASLW, a1: C_U15CON, a6: C_REG, type_: 57, size: 4}, {as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4}, {as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, - {as: ASRAW, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 56, size: 4}, - {as: ASRAW, a1: C_SCON, a6: C_REG, type_: 56, size: 4}, + {as: ASRAW, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4}, + {as: ASRAW, a1: C_U15CON, a6: C_REG, type_: 56, size: 4}, {as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4}, {as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4}, - {as: ASRAD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 56, size: 4}, - {as: ASRAD, a1: C_SCON, a6: C_REG, type_: 56, size: 4}, - {as: ARLWNM, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 63, size: 4}, - {as: ARLWNM, a1: C_SCON, a2: C_REG, a3: C_SCON, a4: C_SCON, a6: C_REG, type_: 63, size: 4}, - {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 63, size: 4}, - {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_SCON, a4: C_SCON, a6: C_REG, type_: 63, size: 4}, - {as: ACLRLSLWI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 62, size: 4}, - {as: ARLDMI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 30, size: 4}, - {as: ARLDC, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 29, size: 4}, + {as: ASRAD, a1: C_U15CON, a2: C_REG, a6: C_REG, type_: 56, size: 4}, + {as: ASRAD, a1: C_U15CON, a6: C_REG, type_: 56, size: 4}, + {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4}, + {as: ARLWNM, a1: C_U15CON, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4}, + {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 63, size: 4}, + {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_U15CON, a4: C_U15CON, a6: C_REG, type_: 63, size: 4}, + {as: ACLRLSLWI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 62, size: 4}, + {as: ARLDMI, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 30, size: 4}, + {as: ARLDC, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4}, {as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4}, - {as: ARLDCL, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 29, size: 4}, - {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4}, - {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4}, - {as: ARLDICL, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4}, - {as: ARLDCL, a1: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4}, + {as: ARLDCL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 29, size: 4}, + {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4}, + {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4}, + {as: ARLDICL, a1: C_U15CON, a2: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4}, + {as: ARLDCL, a1: C_REG, a3: C_32CON, a6: C_REG, type_: 14, size: 4}, {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4}, {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4}, {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4}, @@ -232,8 +232,8 @@ var optabBase = []Optab{ {as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4}, {as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4}, - {as: AMOVD, a1: C_ADDCON, a6: C_REG, type_: 3, size: 4}, - {as: AMOVD, a1: C_ANDCON, a6: C_REG, type_: 3, size: 4}, + {as: AMOVD, a1: C_S16CON, a6: C_REG, type_: 3, size: 4}, + {as: AMOVD, a1: C_U16CON, a6: C_REG, type_: 3, size: 4}, {as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4}, {as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4}, {as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4}, @@ -245,8 +245,8 @@ var optabBase = []Optab{ {as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4}, {as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4}, - {as: AMOVW, a1: C_ADDCON, a6: C_REG, type_: 3, size: 4}, - {as: AMOVW, a1: C_ANDCON, a6: C_REG, type_: 3, size: 4}, + {as: AMOVW, a1: C_S16CON, a6: C_REG, type_: 3, size: 4}, + {as: AMOVW, a1: C_U16CON, a6: C_REG, type_: 3, size: 4}, {as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4}, {as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4}, {as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4}, @@ -258,7 +258,7 @@ var optabBase = []Optab{ {as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4}, {as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4}, - {as: AFMOVD, a1: C_ADDCON, a6: C_FREG, type_: 24, size: 8}, + {as: AFMOVD, a1: C_S16CON, a6: C_FREG, type_: 24, size: 8}, {as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4}, {as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4}, {as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4}, @@ -275,28 +275,28 @@ var optabBase = []Optab{ {as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4}, {as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4}, {as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4}, - {as: AMOVFL, a1: C_FREG, a3: C_LCON, a6: C_FPSCR, type_: 64, size: 4}, + {as: AMOVFL, a1: C_FREG, a3: C_32CON, a6: C_FPSCR, type_: 64, size: 4}, {as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4}, - {as: AMOVFL, a1: C_LCON, a6: C_FPSCR, type_: 65, size: 4}, + {as: AMOVFL, a1: C_32CON, a6: C_FPSCR, type_: 65, size: 4}, {as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4}, - {as: AMOVFL, a1: C_REG, a6: C_LCON, type_: 69, size: 4}, + {as: AMOVFL, a1: C_REG, a6: C_32CON, type_: 69, size: 4}, {as: ASYSCALL, type_: 5, size: 4}, {as: ASYSCALL, a1: C_REG, type_: 77, size: 12}, - {as: ASYSCALL, a1: C_SCON, type_: 77, size: 12}, + {as: ASYSCALL, a1: C_U15CON, type_: 77, size: 12}, {as: ABEQ, a6: C_BRA, type_: 16, size: 4}, {as: ABEQ, a1: C_CREG, a6: C_BRA, type_: 16, size: 4}, - {as: ABR, a6: C_BRA, type_: 11, size: 4}, // b label - {as: ABR, a6: C_BRAPIC, type_: 11, size: 8}, // b label; nop - {as: ABR, a6: C_LR, type_: 18, size: 4}, // blr - {as: ABR, a6: C_CTR, type_: 18, size: 4}, // bctr - {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4}, // bc bo, bi, label - {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4}, // bclr bo, bi - {as: ABC, a1: C_SCON, a2: C_CRBIT, a3: C_SCON, a6: C_LR, type_: 18, size: 4}, // bclr bo, bi, bh - {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4}, // bcctr bo, bi + {as: ABR, a6: C_BRA, type_: 11, size: 4}, // b label + {as: ABR, a6: C_BRAPIC, type_: 11, size: 8}, // b label; nop + {as: ABR, a6: C_LR, type_: 18, size: 4}, // blr + {as: ABR, a6: C_CTR, type_: 18, size: 4}, // bctr + {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_BRA, type_: 16, size: 4}, // bc bo, bi, label + {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4}, // bclr bo, bi + {as: ABC, a1: C_U15CON, a2: C_CRBIT, a3: C_U15CON, a6: C_LR, type_: 18, size: 4}, // bclr bo, bi, bh + {as: ABC, a1: C_U15CON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4}, // bcctr bo, bi {as: ABDNZ, a6: C_BRA, type_: 16, size: 4}, {as: ASYNC, type_: 46, size: 4}, - {as: AWORD, a1: C_LCON, type_: 40, size: 4}, + {as: AWORD, a1: C_32CON, type_: 40, size: 4}, {as: ADWORD, a1: C_64CON, type_: 31, size: 8}, {as: ADWORD, a1: C_LACON, type_: 31, size: 8}, {as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4}, @@ -312,19 +312,19 @@ var optabBase = []Optab{ {as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16}, {as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12}, {as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12}, - {as: AMTFSB0, a1: C_SCON, type_: 52, size: 4}, + {as: AMTFSB0, a1: C_U15CON, type_: 52, size: 4}, /* Other ISA 2.05+ instructions */ {as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4}, /* population count, x-form */ {as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4}, /* compare byte, x-form */ {as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4}, /* compare equal byte, x-form, ISA 3.0 */ {as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4}, - {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_SCON, type_: 92, size: 4}, /* floating test for sw divide, x-form */ - {as: AFTSQRT, a1: C_FREG, a6: C_SCON, type_: 93, size: 4}, /* floating test for sw square root, x-form */ - {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4}, /* copy/paste facility, x-form */ - {as: ADARN, a1: C_SCON, a6: C_REG, type_: 92, size: 4}, /* deliver random number, x-form */ - {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4}, /* multiply-add high/low doubleword, va-form */ - {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_SCON, a6: C_REG, type_: 94, size: 4}, /* add extended using alternate carry, z23-form */ - {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4}, /* logical ops for condition register bits xl-form */ + {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_U15CON, type_: 92, size: 4}, /* floating test for sw divide, x-form */ + {as: AFTSQRT, a1: C_FREG, a6: C_U15CON, type_: 93, size: 4}, /* floating test for sw square root, x-form */ + {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4}, /* copy/paste facility, x-form */ + {as: ADARN, a1: C_U15CON, a6: C_REG, type_: 92, size: 4}, /* deliver random number, x-form */ + {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4}, /* multiply-add high/low doubleword, va-form */ + {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_U15CON, a6: C_REG, type_: 94, size: 4}, /* add extended using alternate carry, z23-form */ + {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4}, /* logical ops for condition register bits xl-form */ /* Misc ISA 3.0 instructions */ {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4}, @@ -367,7 +367,7 @@ var optabBase = []Optab{ /* Vector shift */ {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector shift, vx-form */ {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector shift algebraic, vx-form */ - {as: AVSOI, a1: C_ANDCON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector shift by octet immediate, va-form */ + {as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector shift by octet immediate, va-form */ /* Vector count */ {as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4}, /* vector count leading zeros, vx-form */ @@ -391,10 +391,10 @@ var optabBase = []Optab{ {as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector select, va-form */ /* Vector splat */ - {as: AVSPLTB, a1: C_SCON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector splat, vx-form */ - {as: AVSPLTB, a1: C_ADDCON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, - {as: AVSPLTISB, a1: C_SCON, a6: C_VREG, type_: 82, size: 4}, /* vector splat immediate, vx-form */ - {as: AVSPLTISB, a1: C_ADDCON, a6: C_VREG, type_: 82, size: 4}, + {as: AVSPLTB, a1: C_U15CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector splat, vx-form */ + {as: AVSPLTB, a1: C_S16CON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, + {as: AVSPLTISB, a1: C_U15CON, a6: C_VREG, type_: 82, size: 4}, /* vector splat immediate, vx-form */ + {as: AVSPLTISB, a1: C_S16CON, a6: C_VREG, type_: 82, size: 4}, /* Vector AES */ {as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector AES cipher, vx-form */ @@ -402,7 +402,7 @@ var optabBase = []Optab{ {as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector AES subbytes, vx-form */ /* Vector SHA */ - {as: AVSHASIGMA, a1: C_ANDCON, a2: C_VREG, a3: C_ANDCON, a6: C_VREG, type_: 82, size: 4}, /* vector SHA sigma, vx-form */ + {as: AVSHASIGMA, a1: C_U16CON, a2: C_VREG, a3: C_U16CON, a6: C_VREG, type_: 82, size: 4}, /* vector SHA sigma, vx-form */ /* VSX vector load */ {as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4}, /* vsx vector load, xx1-form */ @@ -446,14 +446,14 @@ var optabBase = []Optab{ {as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx merge, xx3-form */ /* VSX splat */ - {as: AXXSPLTW, a1: C_VSREG, a3: C_SCON, a6: C_VSREG, type_: 89, size: 4}, /* vsx splat, xx2-form */ - {as: AXXSPLTIB, a1: C_SCON, a6: C_VSREG, type_: 100, size: 4}, /* vsx splat, xx2-form */ + {as: AXXSPLTW, a1: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 89, size: 4}, /* vsx splat, xx2-form */ + {as: AXXSPLTIB, a1: C_U15CON, a6: C_VSREG, type_: 100, size: 4}, /* vsx splat, xx2-form */ /* VSX permute */ {as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4}, /* vsx permute, xx3-form */ /* VSX shift */ - {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_SCON, a6: C_VSREG, type_: 90, size: 4}, /* vsx shift immediate, xx3-form */ + {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_U15CON, a6: C_VSREG, type_: 90, size: 4}, /* vsx shift immediate, xx3-form */ /* VSX reverse bytes */ {as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4}, /* vsx reverse bytes */ @@ -478,45 +478,45 @@ var optabBase = []Optab{ {as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4}, {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4}, - {as: ACMP, a1: C_REG, a6: C_ADDCON, type_: 71, size: 4}, - {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_ADDCON, type_: 71, size: 4}, + {as: ACMP, a1: C_REG, a6: C_S16CON, type_: 71, size: 4}, + {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_S16CON, type_: 71, size: 4}, {as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4}, {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4}, - {as: ACMPU, a1: C_REG, a6: C_ANDCON, type_: 71, size: 4}, - {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_ANDCON, type_: 71, size: 4}, + {as: ACMPU, a1: C_REG, a6: C_U16CON, type_: 71, size: 4}, + {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_U16CON, type_: 71, size: 4}, {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4}, {as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4}, - {as: ATW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 60, size: 4}, - {as: ATW, a1: C_LCON, a2: C_REG, a6: C_ADDCON, type_: 61, size: 4}, + {as: ATW, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 60, size: 4}, + {as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4}, {as: ADCBF, a1: C_SOREG, type_: 43, size: 4}, {as: ADCBF, a1: C_XOREG, type_: 43, size: 4}, - {as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_SCON, type_: 43, size: 4}, - {as: ADCBF, a1: C_SOREG, a6: C_SCON, type_: 43, size: 4}, - {as: ADCBF, a1: C_XOREG, a6: C_SCON, type_: 43, size: 4}, + {as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4}, + {as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4}, + {as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4}, {as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4}, {as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4}, {as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4}, - {as: ALDAR, a1: C_XOREG, a3: C_ANDCON, a6: C_REG, type_: 45, size: 4}, + {as: ALDAR, a1: C_XOREG, a3: C_U16CON, a6: C_REG, type_: 45, size: 4}, {as: AEIEIO, type_: 46, size: 4}, {as: ATLBIE, a1: C_REG, type_: 49, size: 4}, - {as: ATLBIE, a1: C_SCON, a6: C_REG, type_: 49, size: 4}, + {as: ATLBIE, a1: C_U15CON, a6: C_REG, type_: 49, size: 4}, {as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4}, {as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4}, {as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4}, - {as: ASTSW, a1: C_REG, a3: C_LCON, a6: C_ZOREG, type_: 41, size: 4}, + {as: ASTSW, a1: C_REG, a3: C_32CON, a6: C_ZOREG, type_: 41, size: 4}, {as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4}, - {as: ALSW, a1: C_ZOREG, a3: C_LCON, a6: C_REG, type_: 42, size: 4}, + {as: ALSW, a1: C_ZOREG, a3: C_32CON, a6: C_REG, type_: 42, size: 4}, {as: obj.AUNDEF, type_: 78, size: 4}, - {as: obj.APCDATA, a1: C_LCON, a6: C_LCON, type_: 0, size: 0}, - {as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR, type_: 0, size: 0}, + {as: obj.APCDATA, a1: C_32CON, a6: C_32CON, type_: 0, size: 0}, + {as: obj.AFUNCDATA, a1: C_U15CON, a6: C_ADDR, type_: 0, size: 0}, {as: obj.ANOP, type_: 0, size: 0}, - {as: obj.ANOP, a1: C_LCON, type_: 0, size: 0}, // NOP operand variations added for #40689 - {as: obj.ANOP, a1: C_REG, type_: 0, size: 0}, // to preserve previous behavior + {as: obj.ANOP, a1: C_32CON, type_: 0, size: 0}, // NOP operand variations added for #40689 + {as: obj.ANOP, a1: C_REG, type_: 0, size: 0}, // to preserve previous behavior {as: obj.ANOP, a1: C_FREG, type_: 0, size: 0}, {as: obj.ADUFFZERO, a6: C_BRA, type_: 11, size: 4}, // same as ABR/ABL {as: obj.ADUFFCOPY, a6: C_BRA, type_: 11, size: 4}, // same as ABR/ABL - {as: obj.APCALIGN, a1: C_LCON, type_: 0, size: 0}, // align code + {as: obj.APCALIGN, a1: C_32CON, type_: 0, size: 0}, // align code } // These are opcodes above which may generate different sequences depending on whether prefix opcode support @@ -551,7 +551,7 @@ var prefixableOptab = []PrefixableOptab{ {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8}, - {Optab: Optab{as: AMOVW, a1: C_LCON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8}, + {Optab: Optab{as: AMOVW, a1: C_32CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8}, @@ -573,8 +573,8 @@ var prefixableOptab = []PrefixableOptab{ {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8}, - {Optab: Optab{as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8}, - {Optab: Optab{as: AADD, a1: C_LCON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8}, + {Optab: Optab{as: AADD, a1: C_32CON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8}, + {Optab: Optab{as: AADD, a1: C_32CON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8}, {Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8}, } @@ -954,7 +954,7 @@ func (c *ctxt9) aclass(a *obj.Addr) int { f64 := a.Val.(float64) if f64 == 0 { if math.Signbit(f64) { - return C_ADDCON + return C_S16CON } return C_ZCON } @@ -1113,7 +1113,7 @@ func (c *ctxt9) oplook(p *obj.Prog) *Optab { return &ops[0] } -// Compare two operand types (ex C_REG, or C_SCON) +// Compare two operand types (ex C_REG, or C_U15CON) // and return true if b is compatible with a. // // Argument comparison isn't reflexitive, so care must be taken. @@ -2558,14 +2558,14 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) { a := OP_ADDI if int64(int16(d)) != d { // Operand is 16 bit value with sign bit set - if o.a1 == C_ANDCON { + if o.a1 == C_U16CON { // Needs unsigned 16 bit so use ORI if isZeroOrR0 { o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v)) break } - // With ADDCON, needs signed 16 bit value, fall through to use ADDI - } else if o.a1 != C_ADDCON { + // With S16CON, needs signed 16 bit value, fall through to use ADDI + } else if o.a1 != C_S16CON { log.Fatalf("invalid handling of %v", p) } } @@ -2691,7 +2691,7 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) { case 13: /* mov[bhwd]{z,} r,r */ // This needs to handle "MOV* $0, Rx". This shows up because $0 also - // matches C_REG if r0iszero. This happens because C_REG sorts before C_ANDCON + // matches C_REG if r0iszero. This happens because C_REG sorts before C_U16CON // TODO: fix the above behavior and cleanup this exception. if p.From.Type == obj.TYPE_CONST { o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0) @@ -2923,8 +2923,8 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) { r = int(p.To.Reg) } - // With ADDCON operand, generate 2 instructions using ADDI for signed value, - // with LCON operand generate 3 instructions. + // With S16CON operand, generate 2 instructions using ADDI for signed value, + // with 32CON operand generate 3 instructions. if o.size == 8 { o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d))) o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) -- 2.48.1