From 47fd73a51c52d58147f164317fc1f5640055bbad Mon Sep 17 00:00:00 2001 From: Xiaolin Zhao Date: Thu, 19 Dec 2024 19:03:43 +0800 Subject: [PATCH] cmd/internal/obj/loong64: add {V,XV}{SLL/SRL/SRA/ROTR}[I].{B/H/W/D} instructions support Go asm syntax: V{SLL/SRL/SRA/ROTR}{B/H/W/V} $1, V2, V3 XV{SLL/SRL/SRA/ROTR}{B/H/W/V} $1, X2, X3 V{SLL/SRL/SRA/ROTR}{B/H/W/V} VK, VJ, VD XV{SLL/SRL/SRA/ROTR}{B/H/W/V} XK, XJ, XD Equivalent platform assembler syntax: v{sll/srl/sra/rotr}i.{b/h/w/d} v3, v2, $1 xv{sll/srl/sra/rotr}i.{b/h/w/d} x3, x2, $1 v{sll/srl/sra/rotr}.{b/h/w/d} vd, vj, vk xv{sll/srl/sra/rotr}.{b/h/w/d} xd, xj, xk Change-Id: Ie4f04de1c77491a71688d226f7d91cd1a699ab47 Reviewed-on: https://go-review.googlesource.com/c/go/+/637775 LUCI-TryBot-Result: Go LUCI Reviewed-by: Meidan Li Reviewed-by: abner chenc Reviewed-by: Junyang Shao Reviewed-by: Michael Pratt --- .../asm/internal/asm/testdata/loong64enc1.s | 130 +++++++++ src/cmd/internal/obj/loong64/a.out.go | 34 +++ src/cmd/internal/obj/loong64/anames.go | 32 +++ src/cmd/internal/obj/loong64/asm.go | 252 ++++++++++++++++++ 4 files changed, 448 insertions(+) diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index 1f0ec9140d..1d34088096 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -540,3 +540,133 @@ lable2: // AND C_SCON, [r1], r2 AND $0x321, R4 // AND $801, R4 // 84844c03 AND $0x321, R5, R4 // AND $801, R5, R4 // a4844c03 + + // [X]{VSLL/VSRL/VSRA/VROTR}{B,H,W,V} instructions + VSLLB V1, V2, V3 // 4304e870 + VSLLH V1, V2, V3 // 4384e870 + VSLLW V1, V2, V3 // 4304e970 + VSLLV V1, V2, V3 // 4384e970 + VSRLB V1, V2, V3 // 4304ea70 + VSRLH V1, V2, V3 // 4384ea70 + VSRLW V1, V2, V3 // 4304eb70 + VSRLV V1, V2, V3 // 4384eb70 + VSRAB V1, V2, V3 // 4304ec70 + VSRAH V1, V2, V3 // 4384ec70 + VSRAW V1, V2, V3 // 4304ed70 + VSRAV V1, V2, V3 // 4384ed70 + VROTRB V1, V2, V3 // 4304ee70 + VROTRH V1, V2, V3 // 4384ee70 + VROTRW V1, V2, V3 // 4304ef70 + VROTRV V1, V2, V3 // 4384ef70 + XVSLLB X3, X2, X1 // 410ce874 + XVSLLH X3, X2, X1 // 418ce874 + XVSLLW X3, X2, X1 // 410ce974 + XVSLLV X3, X2, X1 // 418ce974 + XVSRLB X3, X2, X1 // 410cea74 + XVSRLH X3, X2, X1 // 418cea74 + XVSRLW X3, X2, X1 // 410ceb74 + XVSRLV X3, X2, X1 // 418ceb74 + XVSRAB X3, X2, X1 // 410cec74 + XVSRAH X3, X2, X1 // 418cec74 + XVSRAW X3, X2, X1 // 410ced74 + XVSRAV X3, X2, X1 // 418ced74 + XVROTRB X3, X2, X1 // 410cee74 + XVROTRH X3, X2, X1 // 418cee74 + XVROTRW X3, X2, X1 // 410cef74 + XVROTRV X3, X2, X1 // 418cef74 + VSLLB $0, V1, V2 // 22202c73 + VSLLB $7, V1, V2 // 223c2c73 + VSLLB $5, V1 // 21342c73 + VSLLH $0, V1, V2 // 22402c73 + VSLLH $15, V1, V2 // 227c2c73 + VSLLH $10, V1 // 21682c73 + VSLLW $0, V1, V2 // 22802c73 + VSLLW $31, V1, V2 // 22fc2c73 + VSLLW $11, V1 // 21ac2c73 + VSLLV $0, V1, V2 // 22002d73 + VSLLV $63, V1, V2 // 22fc2d73 + VSLLV $30, V1 // 21782d73 + VSRLB $0, V1, V2 // 22203073 + VSRLB $7, V1, V2 // 223c3073 + VSRLB $4, V1 // 21303073 + VSRLH $0, V1, V2 // 22403073 + VSRLH $15, V1, V2 // 227c3073 + VSRLH $9, V1 // 21643073 + VSRLW $0, V1, V2 // 22803073 + VSRLW $31, V1, V2 // 22fc3073 + VSRLW $16, V1 // 21c03073 + VSRLV $0, V1, V2 // 22003173 + VSRLV $63, V1, V2 // 22fc3173 + VSRLV $40, V1 // 21a03173 + VSRAB $0, V1, V2 // 22203473 + VSRAB $7, V1, V2 // 223c3473 + VSRAB $6, V1 // 21383473 + VSRAH $0, V1, V2 // 22403473 + VSRAH $15, V1, V2 // 227c3473 + VSRAH $8, V1 // 21603473 + VSRAW $0, V1, V2 // 22803473 + VSRAW $31, V1, V2 // 22fc3473 + VSRAW $12, V1 // 21b03473 + VSRAV $0, V1, V2 // 22003573 + VSRAV $63, V1, V2 // 22fc3573 + VSRAV $50, V1 // 21c83573 + VROTRB $0, V1, V2 // 2220a072 + VROTRB $7, V1, V2 // 223ca072 + VROTRB $3, V1 // 212ca072 + VROTRH $0, V1, V2 // 2240a072 + VROTRH $15, V1, V2 // 227ca072 + VROTRH $5, V1 // 2154a072 + VROTRW $0, V1, V2 // 2280a072 + VROTRW $31, V1, V2 // 22fca072 + VROTRW $18, V1 // 21c8a072 + VROTRV $0, V1, V2 // 2200a172 + VROTRV $63, V1, V2 // 22fca172 + VROTRV $52, V1 // 21d0a172 + XVSLLB $0, X2, X1 // 41202c77 + XVSLLB $7, X2, X1 // 413c2c77 + XVSLLB $4, X2 // 42302c77 + XVSLLH $0, X2, X1 // 41402c77 + XVSLLH $15, X2, X1 // 417c2c77 + XVSLLH $8, X2 // 42602c77 + XVSLLW $0, X2, X1 // 41802c77 + XVSLLW $31, X2, X1 // 41fc2c77 + XVSLLW $13, X2 // 42b42c77 + XVSLLV $0, X2, X1 // 41002d77 + XVSLLV $63, X2, X1 // 41fc2d77 + XVSLLV $36, X2 // 42902d77 + XVSRLB $0, X2, X1 // 41203077 + XVSRLB $7, X2, X1 // 413c3077 + XVSRLB $5, X2 // 42343077 + XVSRLH $0, X2, X1 // 41403077 + XVSRLH $15, X2, X1 // 417c3077 + XVSRLH $9, X2 // 42643077 + XVSRLW $0, X2, X1 // 41803077 + XVSRLW $31, X2, X1 // 41fc3077 + XVSRLW $14, X2 // 42b83077 + XVSRLV $0, X2, X1 // 41003177 + XVSRLV $63, X2, X1 // 41fc3177 + XVSRLV $45, X2 // 42b43177 + XVSRAB $0, X2, X1 // 41203477 + XVSRAB $7, X2, X1 // 413c3477 + XVSRAB $6, X2 // 42383477 + XVSRAH $0, X2, X1 // 41403477 + XVSRAH $15, X2, X1 // 417c3477 + XVSRAH $10, X2 // 42683477 + XVSRAW $0, X2, X1 // 41803477 + XVSRAW $31, X2, X1 // 41fc3477 + XVSRAW $16, X2 // 42c03477 + XVSRAV $0, X2, X1 // 41003577 + XVSRAV $63, X2, X1 // 41fc3577 + XVSRAV $48, X2 // 42c03577 + XVROTRB $0, X2, X1 // 4120a076 + XVROTRB $7, X2, X1 // 413ca076 + XVROTRB $3, X2 // 422ca076 + XVROTRH $0, X2, X1 // 4140a076 + XVROTRH $15, X2, X1 // 417ca076 + XVROTRH $13, X2 // 4274a076 + XVROTRW $0, X2, X1 // 4180a076 + XVROTRW $31, X2, X1 // 41fca076 + XVROTRW $24, X2 // 42e0a076 + XVROTRV $0, X2, X1 // 4100a176 + XVROTRV $63, X2, X1 // 41fca176 + XVROTRV $52, X2 // 42d0a176 diff --git a/src/cmd/internal/obj/loong64/a.out.go b/src/cmd/internal/obj/loong64/a.out.go index ef9a3fd5c1..6660ab3b38 100644 --- a/src/cmd/internal/obj/loong64/a.out.go +++ b/src/cmd/internal/obj/loong64/a.out.go @@ -759,6 +759,40 @@ const ( AVSEQV AXVSEQV + // LSX and LASX shift operation instructions + AVSLLB + AVSLLH + AVSLLW + AVSLLV + AVSRLB + AVSRLH + AVSRLW + AVSRLV + AVSRAB + AVSRAH + AVSRAW + AVSRAV + AVROTRB + AVROTRH + AVROTRW + AVROTRV + AXVSLLB + AXVSLLH + AXVSLLW + AXVSLLV + AXVSRLB + AXVSRLH + AXVSRLW + AXVSRLV + AXVSRAB + AXVSRAH + AXVSRAW + AXVSRAV + AXVROTRB + AXVROTRH + AXVROTRW + AXVROTRV + ALAST // aliases diff --git a/src/cmd/internal/obj/loong64/anames.go b/src/cmd/internal/obj/loong64/anames.go index 3d2f329917..bf17058ce6 100644 --- a/src/cmd/internal/obj/loong64/anames.go +++ b/src/cmd/internal/obj/loong64/anames.go @@ -273,5 +273,37 @@ var Anames = []string{ "XVSEQW", "VSEQV", "XVSEQV", + "VSLLB", + "VSLLH", + "VSLLW", + "VSLLV", + "VSRLB", + "VSRLH", + "VSRLW", + "VSRLV", + "VSRAB", + "VSRAH", + "VSRAW", + "VSRAV", + "VROTRB", + "VROTRH", + "VROTRW", + "VROTRV", + "XVSLLB", + "XVSLLH", + "XVSLLW", + "XVSLLV", + "XVSRLB", + "XVSRLH", + "XVSRLW", + "XVSRLV", + "XVSRAB", + "XVSRAH", + "XVSRAW", + "XVSRAV", + "XVROTRB", + "XVROTRH", + "XVROTRW", + "XVROTRV", "LAST", } diff --git a/src/cmd/internal/obj/loong64/asm.go b/src/cmd/internal/obj/loong64/asm.go index e6d07cc0f4..5a5b31ab2f 100644 --- a/src/cmd/internal/obj/loong64/asm.go +++ b/src/cmd/internal/obj/loong64/asm.go @@ -89,6 +89,42 @@ var optab = []Optab{ {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0}, + {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0}, + {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0}, + {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0}, + + {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0}, + {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0}, + {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0}, + {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0}, + + {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, + {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0}, + {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0}, + + {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0}, + {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0}, + {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0}, + {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0}, + {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0}, + {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0}, {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0}, @@ -1509,6 +1545,46 @@ func buildop(ctxt *obj.Link) { opset(AXVPCNTH, r0) opset(AXVPCNTW, r0) opset(AXVPCNTV, r0) + + case AVSLLB: + opset(AVSRLB, r0) + opset(AVSRAB, r0) + opset(AVROTRB, r0) + + case AXVSLLB: + opset(AXVSRLB, r0) + opset(AXVSRAB, r0) + opset(AXVROTRB, r0) + + case AVSLLH: + opset(AVSRLH, r0) + opset(AVSRAH, r0) + opset(AVROTRH, r0) + + case AXVSLLH: + opset(AXVSRLH, r0) + opset(AXVSRAH, r0) + opset(AXVROTRH, r0) + + case AVSLLW: + opset(AVSRLW, r0) + opset(AVSRAW, r0) + opset(AVROTRW, r0) + + case AXVSLLW: + opset(AXVSRLW, r0) + opset(AXVSRAW, r0) + opset(AXVROTRW, r0) + + case AVSLLV: + opset(AVSRLV, r0) + opset(AVSRAV, r0) + opset(AVROTRV, r0) + + case AXVSLLV: + opset(AXVSRLV, r0) + opset(AXVSRAV, r0) + opset(AXVROTRV, r0) } } } @@ -1542,6 +1618,22 @@ func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 { return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0 } +func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 { + return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0 +} + +func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 { + return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0 +} + +func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 { + return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0 +} + +func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 { + return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0 +} + func OP_IR(op uint32, i uint32, r2 uint32) uint32 { return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0 // ui20, rd5 } @@ -1729,6 +1821,22 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { c.ctxt.Diag("unexpected encoding\n%v", p) } + case 13: // vsll $ui3, [vr1], vr2 + v := c.regoff(&p.From) + r := int(p.Reg) + if r == 0 { + r = int(p.To.Reg) + } + o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) + + case 14: // vsll $ui4, [vr1], vr2 + v := c.regoff(&p.From) + r := int(p.Reg) + if r == 0 { + r = int(p.To.Reg) + } + o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) + case 15: // teq $c r,r v := c.regoff(&p.From) r := int(p.Reg) @@ -1879,6 +1987,22 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) { a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To)) o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg)) + case 31: // vsll $ui5, [vr1], vr2 + v := c.regoff(&p.From) + r := int(p.Reg) + if r == 0 { + r = int(p.To.Reg) + } + o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) + + case 32: // vsll $ui6, [vr1], vr2 + v := c.regoff(&p.From) + r := int(p.Reg) + if r == 0 { + r = int(p.To.Reg) + } + o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) + case 34: // mov $con,fr v := c.regoff(&p.From) a := AADDU @@ -2579,6 +2703,70 @@ func (c *ctxt0) oprrr(a obj.As) uint32 { return 0x0e003 << 15 // vseq.d case AXVSEQV: return 0x0e803 << 15 // xvseq.d + case AVSLLB: + return 0xe1d0 << 15 // vsll.b + case AVSLLH: + return 0xe1d1 << 15 // vsll.h + case AVSLLW: + return 0xe1d2 << 15 // vsll.w + case AVSLLV: + return 0xe1d3 << 15 // vsll.d + case AVSRLB: + return 0xe1d4 << 15 // vsrl.b + case AVSRLH: + return 0xe1d5 << 15 // vsrl.h + case AVSRLW: + return 0xe1d6 << 15 // vsrl.w + case AVSRLV: + return 0xe1d7 << 15 // vsrl.d + case AVSRAB: + return 0xe1d8 << 15 // vsra.b + case AVSRAH: + return 0xe1d9 << 15 // vsra.h + case AVSRAW: + return 0xe1da << 15 // vsra.w + case AVSRAV: + return 0xe1db << 15 // vsra.d + case AVROTRB: + return 0xe1dc << 15 // vrotr.b + case AVROTRH: + return 0xe1dd << 15 // vrotr.h + case AVROTRW: + return 0xe1de << 15 // vrotr.w + case AVROTRV: + return 0xe1df << 15 // vrotr.d + case AXVSLLB: + return 0xe9d0 << 15 // xvsll.b + case AXVSLLH: + return 0xe9d1 << 15 // xvsll.h + case AXVSLLW: + return 0xe9d2 << 15 // xvsll.w + case AXVSLLV: + return 0xe9d3 << 15 // xvsll.d + case AXVSRLB: + return 0xe9d4 << 15 // xvsrl.b + case AXVSRLH: + return 0xe9d5 << 15 // xvsrl.h + case AXVSRLW: + return 0xe9d6 << 15 // xvsrl.w + case AXVSRLV: + return 0xe9d7 << 15 // xvsrl.d + case AXVSRAB: + return 0xe9d8 << 15 // xvsra.b + case AXVSRAH: + return 0xe9d9 << 15 // xvsra.h + case AXVSRAW: + return 0xe9da << 15 // xvsra.w + case AXVSRAV: + return 0xe9db << 15 // xvsra.d + case AXVROTRB: + return 0xe9dc << 15 // xvrotr.b + case AXVROTRH: + return 0xe9dd << 15 // xvrotr.h + case AXVROTRW: + return 0xe9de << 15 // xvrotr.w + case AXVROTRV: + return 0xe9df << 15 // xvrotr.d } if a < 0 { @@ -2906,6 +3094,70 @@ func (c *ctxt0) opirr(a obj.As) uint32 { return 0x021 << 24 case ASCV: return 0x023 << 24 + case AVROTRB: + return 0x1ca8<<18 | 0x1<<13 // vrotri.b + case AVROTRH: + return 0x1ca8<<18 | 0x1<<14 // vrotri.h + case AVROTRW: + return 0x1ca8<<18 | 0x1<<15 // vrotri.w + case AVROTRV: + return 0x1ca8<<18 | 0x1<<16 // vrotri.d + case AXVROTRB: + return 0x1da8<<18 | 0x1<<13 // xvrotri.b + case AXVROTRH: + return 0x1da8<<18 | 0x1<<14 // xvrotri.h + case AXVROTRW: + return 0x1da8<<18 | 0x1<<15 // xvrotri.w + case AXVROTRV: + return 0x1da8<<18 | 0x1<<16 // xvrotri.d + case AVSLLB: + return 0x1ccb<<18 | 0x1<<13 // vslli.b + case AVSLLH: + return 0x1ccb<<18 | 0x1<<14 // vslli.h + case AVSLLW: + return 0x1ccb<<18 | 0x1<<15 // vslli.w + case AVSLLV: + return 0x1ccb<<18 | 0x1<<16 // vslli.d + case AVSRLB: + return 0x1ccc<<18 | 0x1<<13 // vsrli.b + case AVSRLH: + return 0x1ccc<<18 | 0x1<<14 // vsrli.h + case AVSRLW: + return 0x1ccc<<18 | 0x1<<15 // vsrli.w + case AVSRLV: + return 0x1ccc<<18 | 0x1<<16 // vsrli.d + case AVSRAB: + return 0x1ccd<<18 | 0x1<<13 // vsrai.b + case AVSRAH: + return 0x1ccd<<18 | 0x1<<14 // vsrai.h + case AVSRAW: + return 0x1ccd<<18 | 0x1<<15 // vsrai.w + case AVSRAV: + return 0x1ccd<<18 | 0x1<<16 // vsrai.d + case AXVSLLB: + return 0x1dcb<<18 | 0x1<<13 // xvslli.b + case AXVSLLH: + return 0x1dcb<<18 | 0x1<<14 // xvslli.h + case AXVSLLW: + return 0x1dcb<<18 | 0x1<<15 // xvslli.w + case AXVSLLV: + return 0x1dcb<<18 | 0x1<<16 // xvslli.d + case AXVSRLB: + return 0x1dcc<<18 | 0x1<<13 // xvsrli.b + case AXVSRLH: + return 0x1dcc<<18 | 0x1<<14 // xvsrli.h + case AXVSRLW: + return 0x1dcc<<18 | 0x1<<15 // xvsrli.w + case AXVSRLV: + return 0x1dcc<<18 | 0x1<<16 // xvsrli.d + case AXVSRAB: + return 0x1dcd<<18 | 0x1<<13 // xvsrai.b + case AXVSRAH: + return 0x1dcd<<18 | 0x1<<14 // xvsrai.h + case AXVSRAW: + return 0x1dcd<<18 | 0x1<<15 // xvsrai.w + case AXVSRAV: + return 0x1dcd<<18 | 0x1<<16 // xvsrai.d } if a < 0 { -- 2.51.0