From 8f14f33f96d35416786d65664ca731ae75d1c733 Mon Sep 17 00:00:00 2001
From: Joel Sing <joel@sing.id.au>
Date: Mon, 27 Jan 2020 23:55:30 +1100
Subject: [PATCH] cmd/compile/internal/ssa/gen: avoid importing internal
 riscv64 packages

Duplicate the register definitions and names to avoid importing the
cmd/internal/obj/riscv64 package. This makes it possible to build compiler rules
with a stable Go tool chain.

Fixes #36663

Change-Id: I09116a97bb037ca1bc00073306a82bb88862b1e9
Reviewed-on: https://go-review.googlesource.com/c/go/+/216518
Reviewed-by: Cherry Zhang <cherryyz@google.com>
---
 .../compile/internal/ssa/gen/RISCV64Ops.go    | 40 +++++++++++++++----
 1 file changed, 33 insertions(+), 7 deletions(-)

diff --git a/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go b/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
index a251146c2a..88a97e43fd 100644
--- a/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
+++ b/src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
@@ -6,7 +6,9 @@
 
 package main
 
-import "cmd/internal/obj/riscv"
+import (
+	"fmt"
+)
 
 // Suffixes encode the bit width of various instructions:
 //
@@ -18,6 +20,30 @@ import "cmd/internal/obj/riscv"
 // D (double)      = 64 bit float
 // L               = 64 bit int, used when the opcode starts with F
 
+const (
+	riscv64REG_G    = 4
+	riscv64REG_CTXT = 20
+	riscv64REG_LR   = 1
+	riscv64REG_SP   = 2
+	riscv64REG_TMP  = 31
+	riscv64REG_ZERO = 0
+)
+
+func riscv64RegName(r int) string {
+	switch {
+	case r == riscv64REG_G:
+		return "g"
+	case r == riscv64REG_SP:
+		return "SP"
+	case 0 <= r && r <= 31:
+		return fmt.Sprintf("X%d", r)
+	case 32 <= r && r <= 63:
+		return fmt.Sprintf("F%d", r-32)
+	default:
+		panic(fmt.Sprintf("unknown register %d", r))
+	}
+}
+
 func init() {
 	var regNamesRISCV64 []string
 	var gpMask, fpMask, gpspMask, gpspsbMask regMask
@@ -30,7 +56,7 @@ func init() {
 	addreg := func(r int, name string) regMask {
 		mask := regMask(1) << uint(len(regNamesRISCV64))
 		if name == "" {
-			name = riscv.RegName(r)
+			name = riscv64RegName(r)
 		}
 		regNamesRISCV64 = append(regNamesRISCV64, name)
 		regNamed[name] = mask
@@ -38,8 +64,8 @@ func init() {
 	}
 
 	// General purpose registers.
-	for r := riscv.REG_X0; r <= riscv.REG_X31; r++ {
-		if r == riscv.REG_LR {
+	for r := 0; r <= 31; r++ {
+		if r == riscv64REG_LR {
 			// LR is not used by regalloc, so we skip it to leave
 			// room for pseudo-register SB.
 			continue
@@ -50,8 +76,8 @@ func init() {
 		// Add general purpose registers to gpMask.
 		switch r {
 		// ZERO, g, and TMP are not in any gp mask.
-		case riscv.REG_ZERO, riscv.REG_G, riscv.REG_TMP:
-		case riscv.REG_SP:
+		case riscv64REG_ZERO, riscv64REG_G, riscv64REG_TMP:
+		case riscv64REG_SP:
 			gpspMask |= mask
 			gpspsbMask |= mask
 		default:
@@ -62,7 +88,7 @@ func init() {
 	}
 
 	// Floating pointer registers.
-	for r := riscv.REG_F0; r <= riscv.REG_F31; r++ {
+	for r := 32; r <= 63; r++ {
 		mask := addreg(r, "")
 		fpMask |= mask
 	}
-- 
2.50.0