From 9735fcfce78360eeaaa62fb44bd597f7b85ff429 Mon Sep 17 00:00:00 2001 From: Elias Naur Date: Sun, 1 Oct 2017 12:51:54 +0200 Subject: [PATCH] sync/atomic: add memory barriers to Load/StoreInt32 on darwin/arm After switching to an iPhone 5 for the darwin/arm builds, TestStoreLoadRelAcq32 started to timeout on every builder run. Adding the same memory barriers as armLoadUint64 and armStoreUint64 makes the test complete successfully. Fixes sync/atomic tests on the darwin/arm builder. Change-Id: Id73de31679304e259bdbd7f2f94383ae7fd70ee4 Reviewed-on: https://go-review.googlesource.com/67390 TryBot-Result: Gobot Gobot Reviewed-by: Dmitry Vyukov --- src/sync/atomic/asm_darwin_arm.s | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/sync/atomic/asm_darwin_arm.s b/src/sync/atomic/asm_darwin_arm.s index c64336034d..226822926f 100644 --- a/src/sync/atomic/asm_darwin_arm.s +++ b/src/sync/atomic/asm_darwin_arm.s @@ -6,6 +6,12 @@ // Darwin/ARM atomic operations. +#define DMB_ISHST_7 \ + WORD $0xf57ff05a // dmb ishst + +#define DMB_ISH_7 \ + WORD $0xf57ff05b // dmb ish + TEXT ·CompareAndSwapInt32(SB),NOSPLIT,$0 B ·CompareAndSwapUint32(SB) @@ -58,9 +64,11 @@ TEXT ·LoadUint32(SB),NOSPLIT,$0-8 MOVW addr+0(FP), R1 load32loop: LDREX (R1), R2 // loads R2 + DMB_ISHST_7 STREX R2, (R1), R0 // stores R2 CMP $0, R0 BNE load32loop + DMB_ISH_7 MOVW R2, val+4(FP) RET @@ -84,9 +92,11 @@ TEXT ·StoreUint32(SB),NOSPLIT,$0-8 MOVW val+4(FP), R2 storeloop: LDREX (R1), R4 // loads R4 + DMB_ISHST_7 STREX R2, (R1), R0 // stores R2 CMP $0, R0 BNE storeloop + DMB_ISH_7 RET TEXT ·StoreInt64(SB),NOSPLIT,$0 -- 2.48.1