From 99f811ecca5674a6e6f423b97ea79f0a6eedf4b6 Mon Sep 17 00:00:00 2001 From: "Paul E. Murphy" Date: Mon, 27 Feb 2023 16:05:34 -0600 Subject: [PATCH] cmd/internal/obj/ppc64: add SETB instruction This ISA 3.0 (power9) instruction is helpful for some string functions in a future change. Change-Id: I1a659488ffb5099f8c89f480c39af4ef9c4b556a Reviewed-on: https://go-review.googlesource.com/c/go/+/472635 Reviewed-by: Dmitri Shuralyov Reviewed-by: Archana Ravindar Reviewed-by: Carlos Amedee Reviewed-by: Lynn Boger Run-TryBot: Paul Murphy TryBot-Result: Gopher Robot --- src/cmd/asm/internal/asm/testdata/ppc64.s | 2 ++ src/cmd/internal/obj/ppc64/a.out.go | 1 + src/cmd/internal/obj/ppc64/anames.go | 1 + src/cmd/internal/obj/ppc64/asm9.go | 10 ++++++++++ 4 files changed, 14 insertions(+) diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s index 72ae796018..7a83fb952b 100644 --- a/src/cmd/asm/internal/asm/testdata/ppc64.s +++ b/src/cmd/asm/internal/asm/testdata/ppc64.s @@ -1087,4 +1087,6 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVD 4(R1), XER // ebe100047fe103a6 PNOP // 0700000000000000 + SETB CR1,R3 // 7c640100 + RET diff --git a/src/cmd/internal/obj/ppc64/a.out.go b/src/cmd/internal/obj/ppc64/a.out.go index 995f9d9b0a..09b0a87a07 100644 --- a/src/cmd/internal/obj/ppc64/a.out.go +++ b/src/cmd/internal/obj/ppc64/a.out.go @@ -801,6 +801,7 @@ const ( AEXTSWSLICC ASTDCCC ATD + ASETB /* 64-bit pseudo operation */ ADWORD diff --git a/src/cmd/internal/obj/ppc64/anames.go b/src/cmd/internal/obj/ppc64/anames.go index 05014ecfde..81e1fd1ea4 100644 --- a/src/cmd/internal/obj/ppc64/anames.go +++ b/src/cmd/internal/obj/ppc64/anames.go @@ -333,6 +333,7 @@ var Anames = []string{ "EXTSWSLICC", "STDCCC", "TD", + "SETB", "DWORD", "REMD", "REMDU", diff --git a/src/cmd/internal/obj/ppc64/asm9.go b/src/cmd/internal/obj/ppc64/asm9.go index 40258ca0b2..799def6ef7 100644 --- a/src/cmd/internal/obj/ppc64/asm9.go +++ b/src/cmd/internal/obj/ppc64/asm9.go @@ -325,6 +325,9 @@ var optab = []Optab{ {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_SCON, a6: C_REG, type_: 94, size: 4}, /* add extended using alternate carry, z23-form */ {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4}, /* logical ops for condition register bits xl-form */ + /* Misc ISA 3.0 instructions */ + {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4}, + /* Vector instructions */ /* Vector load */ @@ -2111,6 +2114,7 @@ func buildop(ctxt *obj.Link) { AMTVSRDD, APNOP, AISEL, + ASETB, obj.ANOP, obj.ATEXT, obj.AUNDEF, @@ -2335,6 +2339,7 @@ const ( OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 OP_EXTSWSLI = 31<<26 | 445<<2 + OP_SETB = 31<<26 | 128<<1 ) func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) { @@ -3971,6 +3976,11 @@ func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) { o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) // Sign extend MOVB operations. This is ignored for other cases (o.size == 4). o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) + + case 110: /* SETB creg, rt */ + bfa := uint32(p.From.Reg) << 2 + rt := uint32(p.To.Reg) + o1 = LOP_RRR(OP_SETB, bfa, rt, 0) } out[0] = o1 -- 2.50.0