From 9e8020b2d4a4730a7b2c75a0091473dc7583959b Mon Sep 17 00:00:00 2001 From: Nick Ripley Date: Fri, 17 Jun 2022 16:33:14 -0400 Subject: [PATCH] cmd/asm: add VTBX instruction on arm64 Change-Id: Icd9eeb78bfc0c0bbe19dcb9841c9fdc0abc29cc9 Reviewed-on: https://go-review.googlesource.com/c/go/+/413314 TryBot-Result: Gopher Robot Reviewed-by: Than McIntosh Run-TryBot: Cherry Mui Reviewed-by: Cherry Mui --- src/cmd/asm/internal/arch/arm64.go | 2 +- src/cmd/asm/internal/asm/testdata/arm64.s | 16 ++++++++++++++++ src/cmd/internal/obj/arm64/a.out.go | 1 + src/cmd/internal/obj/arm64/anames.go | 1 + src/cmd/internal/obj/arm64/asm7.go | 15 ++++++++++++--- 5 files changed, 31 insertions(+), 4 deletions(-) diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go index 936b894a22..e426814aab 100644 --- a/src/cmd/asm/internal/arch/arm64.go +++ b/src/cmd/asm/internal/arch/arm64.go @@ -131,7 +131,7 @@ func IsARM64STLXR(op obj.As) bool { // inputs does not fit into prog.Reg, so require special handling. func IsARM64TBL(op obj.As) bool { switch op { - case arm64.AVTBL, arm64.AVMOVQ: + case arm64.AVTBL, arm64.AVTBX, arm64.AVMOVQ: return true } return false diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 4451338d51..edd7a98279 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -167,6 +167,22 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VTBL V14.B16, [V3.B16, V4.B16, V5.B16], V17.B16 // 71400e4e VTBL V13.B16, [V29.B16, V30.B16, V31.B16, V0.B16], V28.B16 // bc630d4e VTBL V3.B8, [V27.B16], V8.B8 // 6803030e + VTBX V22.B16, [V28.B16, V29.B16], V11.B16 // 8b33164e + VTBX V18.B8, [V17.B16, V18.B16, V19.B16], V22.B8 // 3652120e + VTBX V31.B8, [V14.B16, V15.B16, V16.B16, V17.B16], V15.B8 // cf711f0e + VTBX V14.B16, [V16.B16], V11.B16 // 0b120e4e + VTBX V28.B16, [V25.B16, V26.B16], V5.B16 // 25331c4e + VTBX V16.B8, [V4.B16, V5.B16, V6.B16], V12.B8 // 8c50100e + VTBX V4.B8, [V16.B16, V17.B16, V18.B16, V19.B16], V4.B8 // 0472040e + VTBX V15.B8, [V1.B16], V20.B8 // 34100f0e + VTBX V26.B16, [V2.B16, V3.B16], V26.B16 // 5a301a4e + VTBX V15.B8, [V6.B16, V7.B16, V8.B16], V2.B8 // c2500f0e + VTBX V2.B16, [V27.B16, V28.B16, V29.B16, V30.B16], V18.B16 // 7273024e + VTBX V11.B16, [V13.B16], V27.B16 // bb110b4e + VTBX V3.B8, [V7.B16, V8.B16], V25.B8 // f930030e + VTBX V14.B16, [V3.B16, V4.B16, V5.B16], V17.B16 // 71500e4e + VTBX V13.B16, [V29.B16, V30.B16, V31.B16, V0.B16], V28.B16 // bc730d4e + VTBX V3.B8, [V27.B16], V8.B8 // 6813030e VZIP1 V16.H8, V3.H8, V19.H8 // 7338504e VZIP2 V22.D2, V25.D2, V21.D2 // 357bd64e VZIP1 V6.D2, V9.D2, V11.D2 // 2b39c64e diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go index d6522f5738..0527fa1ea2 100644 --- a/src/cmd/internal/obj/arm64/a.out.go +++ b/src/cmd/internal/obj/arm64/a.out.go @@ -1009,6 +1009,7 @@ const ( AVBSL AVBIT AVTBL + AVTBX AVXAR AVZIP1 AVZIP2 diff --git a/src/cmd/internal/obj/arm64/anames.go b/src/cmd/internal/obj/arm64/anames.go index ab97a1a130..03222f9c37 100644 --- a/src/cmd/internal/obj/arm64/anames.go +++ b/src/cmd/internal/obj/arm64/anames.go @@ -530,6 +530,7 @@ var Anames = []string{ "VBSL", "VBIT", "VTBL", + "VTBX", "VXAR", "VZIP1", "VZIP2", diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go index c2894a0b9c..b2273de21a 100644 --- a/src/cmd/internal/obj/arm64/asm7.go +++ b/src/cmd/internal/obj/arm64/asm7.go @@ -3154,6 +3154,9 @@ func buildop(ctxt *obj.Link) { case AVUADDW: oprangeset(AVUADDW2, t) + case AVTBL: + oprangeset(AVTBX, t) + case ASHA1H, AVCNT, AVMOV, @@ -3162,7 +3165,6 @@ func buildop(ctxt *obj.Link) { AVST2, AVST3, AVST4, - AVTBL, AVDUP, AVMOVI, APRFM, @@ -5479,7 +5481,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) { rf := int(p.From.Reg) o1 |= uint32(rf & 31) - case 100: /* VTBL Vn., [Vt1., Vt2., ...], Vd. */ + case 100: /* VTBL/VTBX Vn., [Vt1., Vt2., ...], Vd. */ af := int((p.From.Reg >> 5) & 15) at := int((p.To.Reg >> 5) & 15) if af != at { @@ -5510,7 +5512,14 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) { default: c.ctxt.Diag("invalid register numbers in ARM64 register list: %v", p) } - o1 = q<<30 | 0xe<<24 | len<<13 + var op uint32 + switch p.As { + case AVTBL: + op = 0 + case AVTBX: + op = 1 + } + o1 = q<<30 | 0xe<<24 | len<<13 | op<<12 o1 |= (uint32(rf&31) << 16) | uint32(offset&31)<<5 | uint32(rt&31) case 101: // VMOVQ $vcon1, $vcon2, Vd or VMOVD|VMOVS $vcon, Vd -> FMOVQ/FMOVD/FMOVS pool(PC), Vd: load from constant pool. -- 2.50.0