From b5c2b1ec13f324743613bb33cbe6c664974db48e Mon Sep 17 00:00:00 2001 From: Roland Shoemaker Date: Wed, 10 Jul 2024 17:02:34 -0500 Subject: [PATCH] cmd/internal/obj/arm64: support MSR DIT Set the right instruction bits in asmout in order to allow using MSR with DIT and an immediate value. This allows us to avoid using an intermediary register when we want to set DIT (unsetting DIT already worked with the zero register). Ref: https://developer.arm.com/documentation/ddi0602/2024-06/Base-Instructions/MSR--immediate---Move-immediate-value-to-special-register-?lang=en Change-Id: Id049a0b4e0feb534cea992553228f9b5e12ddcea Reviewed-on: https://go-review.googlesource.com/c/go/+/597595 LUCI-TryBot-Result: Go LUCI Reviewed-by: Cherry Mui --- src/cmd/asm/internal/asm/testdata/arm64.s | 1 + src/cmd/internal/obj/arm64/asm7.go | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index f12cdaf921..14a1c9141d 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -1777,6 +1777,7 @@ next: MSR R17, ZCR_EL1 // 111218d5 SYS $32768, R1 // 018008d5 SYS $32768 // 1f8008d5 + MSR $1, DIT // 5f4103d5 // TLBI instruction TLBI VMALLE1IS // 1f8308d5 diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go index c6601cb49e..178c83c0bc 100644 --- a/src/cmd/internal/obj/arm64/asm7.go +++ b/src/cmd/internal/obj/arm64/asm7.go @@ -4229,6 +4229,9 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) { // PSTATEfield can be special registers and special operands. if p.To.Type == obj.TYPE_REG && p.To.Reg == REG_SPSel { v = 0<<16 | 4<<12 | 5<<5 + } else if p.To.Type == obj.TYPE_REG && p.To.Reg == REG_DIT { + // op1 = 011 (3) op2 = 010 (2) + v = 3<<16 | 2<<5 } else if p.To.Type == obj.TYPE_SPECIAL { opd := SpecialOperand(p.To.Offset) for _, pf := range pstatefield { -- 2.48.1