From d3c0af7a0a57480391dcd3a63e2c9450399d2628 Mon Sep 17 00:00:00 2001 From: Alberto Donizetti Date: Mon, 31 Jul 2017 11:38:13 +0200 Subject: [PATCH] cmd/compile: fix ADDSDmem comment and order in list ADDSDmem comment said f32 (likely a copy-paste mistake). Also swap ADDSSmem and ADDSDmem positions in the list to uniform the list order. Fixes #21225 Change-Id: I26bb116900c1cf4c4e6faeef613d7318c9c85b98 Reviewed-on: https://go-review.googlesource.com/52071 Run-TryBot: Alberto Donizetti TryBot-Result: Gobot Gobot Reviewed-by: Ilya Tocar Reviewed-by: Keith Randall --- src/cmd/compile/internal/ssa/gen/AMD64Ops.go | 2 +- src/cmd/compile/internal/ssa/opGen.go | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go index c51cbd2238..df0d13c3f7 100644 --- a/src/cmd/compile/internal/ssa/gen/AMD64Ops.go +++ b/src/cmd/compile/internal/ssa/gen/AMD64Ops.go @@ -179,8 +179,8 @@ func init() { {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by i store {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by 8i store - {name: "ADDSDmem", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem {name: "ADDSSmem", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem + {name: "ADDSDmem", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem {name: "SUBSSmem", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem {name: "SUBSDmem", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem {name: "MULSSmem", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index ae2dd5f550..17a5e70204 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -427,8 +427,8 @@ const ( OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 - OpAMD64ADDSDmem OpAMD64ADDSSmem + OpAMD64ADDSDmem OpAMD64SUBSSmem OpAMD64SUBSDmem OpAMD64MULSSmem @@ -4683,13 +4683,13 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "ADDSDmem", + name: "ADDSSmem", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, - asm: x86.AADDSD, + asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 @@ -4701,13 +4701,13 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "ADDSSmem", + name: "ADDSDmem", auxType: auxSymOff, argLen: 3, resultInArg0: true, faultOnNilArg1: true, symEffect: SymRead, - asm: x86.AADDSS, + asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 -- 2.48.1