From d3d548913570f7b7c1ae2672624607d5831032b1 Mon Sep 17 00:00:00 2001 From: Ben Shi Date: Fri, 9 Jun 2017 10:24:42 +0000 Subject: [PATCH] cmd/internal/obj/arm: fix encoding of move register/immediate to CPSR "MOVW R1, CPSR" is assembled to 0xe129f001, which should be 0xe12cf001. "MOVW $255, CPSR" is assembled to 0xe329f0ff, which should be 0xe32cf0ff. This patch fixes them and adds more assembly encoding tests. fix #20626 Change-Id: Iefc945879ea774edf40438ce39f52c144e1501a1 Reviewed-on: https://go-review.googlesource.com/45170 Reviewed-by: Cherry Zhang --- src/cmd/asm/internal/asm/testdata/arm.s | 31 ++++++++++++++++++++++++- src/cmd/internal/obj/arm/asm5.go | 4 ++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/cmd/asm/internal/asm/testdata/arm.s b/src/cmd/asm/internal/asm/testdata/arm.s index 30d24ac805..20891f0ab6 100644 --- a/src/cmd/asm/internal/asm/testdata/arm.s +++ b/src/cmd/asm/internal/asm/testdata/arm.s @@ -1111,14 +1111,43 @@ jmp_label_3: // MOVW mov_label_0: + MOVW R3, R4 // MOVW R3, R4 // 0340a0e1 + MOVW R9, R2 // MOVW R9, R2 // 0920a0e1 MOVW $0xff, R9 // MOVW $255, R9 // ff90a0e3 MOVW $0xff000000, R9 // MOVW $4278190080, R9 // ff94a0e3 - MOVW R3, R4 // 0340a0e1 MOVW $0xff(R0), R1 // MOVW $255(R0), R1 // ff1080e2 MOVW $-0xff(R0), R1 // MOVW $-255(R0), R1 // ff1040e2 MOVW $0xffffffae, R1 // MOVW $4294967214, R1 // 5110e0e3 MOVW $0xaaaaaaaa, R1 // MOVW $2863311530, R1 MOVW $mov_label_0(SB), R2 // MOVW $mov_label_0(SB), R2 + MOVW R1, (R2) // MOVW R1, (R2) // 001082e5 + MOVW.P R1, (R2) // MOVW.P R1, (R2) // 001082e4 + MOVW.W R1, (R2) // MOVW.W R1, (R2) // 0010a2e5 + MOVW R1, 0x20(R2) // MOVW R1, 32(R2) // 201082e5 + MOVW.P R1, 0x20(R2) // MOVW.P R1, 32(R2) // 201082e4 + MOVW.W R1, 0x20(R2) // MOVW.W R1, 32(R2) // 2010a2e5 + MOVW R1, -0x20(R2) // MOVW R1, -32(R2) // 201002e5 + MOVW.P R1, -0x20(R2) // MOVW.P R1, -32(R2) // 201002e4 + MOVW.W R1, -0x20(R2) // MOVW.W R1, -32(R2) // 201022e5 + MOVW R1, mov_label_0(SB) // MOVW R1, mov_label_0(SB) + MOVW (R2), R1 // MOVW (R2), R1 // 001092e5 + MOVW.P (R2), R1 // MOVW.P (R2), R1 // 001092e4 + MOVW.W (R2), R1 // MOVW.W (R2), R1 // 0010b2e5 + MOVW 0x20(R2), R1 // MOVW 32(R2), R1 // 201092e5 + MOVW.P 0x20(R2), R1 // MOVW.P 32(R2), R1 // 201092e4 + MOVW.W 0x20(R2), R1 // MOVW.W 32(R2), R1 // 2010b2e5 + MOVW -0x20(R2), R1 // MOVW -32(R2), R1 // 201012e5 + MOVW.P -0x20(R2), R1 // MOVW.P -32(R2), R1 // 201012e4 + MOVW.W -0x20(R2), R1 // MOVW.W -32(R2), R1 // 201032e5 + MOVW mov_label_0(SB), R1 // MOVW mov_label_0(SB), R1 + MOVW R1, 0x00ffffff(R2) // MOVW R1, 16777215(R2) + MOVW R1, foo(SB) // MOVW R1, foo(SB) + MOVW 0x00ffffff(R2), R1 // MOVW 16777215(R2), R1 + MOVW foo(SB), R1 // MOVW foo(SB), R1 + MOVW CPSR, R1 // MOVW CPSR, R1 // 00100fe1 + MOVW R1, CPSR // MOVW R1, CPSR // 01f02ce1 + MOVW $0xff, CPSR // MOVW $255, CPSR // fff02ce3 + MOVW $0xff000000, CPSR // MOVW $4278190080, CPSR // fff42ce3 // // END diff --git a/src/cmd/internal/obj/arm/asm5.go b/src/cmd/internal/obj/arm/asm5.go index cee3709eec..ec6867b2a2 100644 --- a/src/cmd/internal/obj/arm/asm5.go +++ b/src/cmd/internal/obj/arm/asm5.go @@ -2066,7 +2066,7 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) { o1 |= (uint32(p.To.Reg) & 15) << 12 case 36: /* mov R,PSR */ - o1 = 2<<23 | 0x29f<<12 | 0<<4 + o1 = 2<<23 | 0x2cf<<12 | 0<<4 if p.Scond&C_FBIT != 0 { o1 ^= 0x010 << 12 @@ -2078,7 +2078,7 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) { case 37: /* mov $con,PSR */ c.aclass(&p.From) - o1 = 2<<23 | 0x29f<<12 | 0<<4 + o1 = 2<<23 | 0x2cf<<12 | 0<<4 if p.Scond&C_FBIT != 0 { o1 ^= 0x010 << 12 } -- 2.48.1