From d7ad7b9efecf034e2d95fe48b455a8dbb2204f2e Mon Sep 17 00:00:00 2001 From: Keith Randall Date: Mon, 4 Jan 2016 13:34:54 -0800 Subject: [PATCH] [dev.ssa] cmd/compile: zero register masks for each edge Forgot to reset these masks before each merge edge is processed. Change-Id: I2f593189b63f50a1cd12b2dd4645ca7b9614f1f3 Reviewed-on: https://go-review.googlesource.com/18223 Reviewed-by: David Chase Run-TryBot: David Chase --- src/cmd/compile/internal/ssa/regalloc.go | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/cmd/compile/internal/ssa/regalloc.go b/src/cmd/compile/internal/ssa/regalloc.go index 0f1068a337..d7c4674cfd 100644 --- a/src/cmd/compile/internal/ssa/regalloc.go +++ b/src/cmd/compile/internal/ssa/regalloc.go @@ -1052,6 +1052,9 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive for k := range e.contents { delete(e.contents, k) } + e.usedRegs = 0 + e.uniqueRegs = 0 + e.finalRegs = 0 // Live registers can be sources. for _, x := range srcReg { @@ -1384,6 +1387,12 @@ func (e *edgeState) findRegFor(typ Type) Location { } } + fmt.Printf("m:%d unique:%d final:%d\n", m, e.uniqueRegs, e.finalRegs) + for vid, a := range e.cache { + for _, c := range a { + fmt.Printf("v%d: %s %s\n", vid, c, e.s.f.getHome(c.ID).Name()) + } + } e.s.f.Fatalf("can't find empty register on edge %s->%s", e.p, e.b) return nil } -- 2.48.1