From f1935c52703e4482c5047b4b35276e965896df7c Mon Sep 17 00:00:00 2001 From: hasheddan Date: Thu, 11 Nov 2021 10:02:13 -0500 Subject: [PATCH] obj/riscv: fix link to risc-v dwarf register numbers The repository name and structure in the RISC-V GitHub org has been modified, rendering the existing link invalid. This updates to point at the new location of the RISC-V DWARF specification. Change occured in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/208 Change-Id: I8ca4c390bee2d7ce20418cdd00e4945a426cf5f7 Reviewed-on: https://go-review.googlesource.com/c/go/+/363355 Reviewed-by: Brad Fitzpatrick Trust: Brad Fitzpatrick Trust: Than McIntosh --- src/cmd/internal/obj/riscv/cpu.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index ed88f621d9..d9434e7415 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -183,7 +183,7 @@ const ( REGG = REG_G ) -// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers +// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers var RISCV64DWARFRegisters = map[int16]int16{ // Integer Registers. REG_X0: 0, -- 2.50.0