From fdf5aaf5555692a9e03a65df1aba06aa4a09052b Mon Sep 17 00:00:00 2001 From: fanzha02 Date: Mon, 5 Mar 2018 07:48:28 +0000 Subject: [PATCH] cmd/asm: fix ARM64 vector register arrangement encoding bug The current code assigns vector register arrangement a wrong value when the arrangement specifier is S2, which causes the incorrect assembly. The patch fixes the issue and adds the test cases. Fixes #24249 Change-Id: I9736df1279494003d0b178da1af9cee9cd85ce21 Reviewed-on: https://go-review.googlesource.com/98555 Reviewed-by: Cherry Zhang Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot --- src/cmd/asm/internal/arch/arm64.go | 2 +- src/cmd/asm/internal/asm/testdata/arm64.s | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go index ca5374b6c0..74b7d285df 100644 --- a/src/cmd/asm/internal/arch/arm64.go +++ b/src/cmd/asm/internal/arch/arm64.go @@ -267,7 +267,7 @@ func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) { curSize = 1 curQ = 1 case "S2": - curSize = 1 + curSize = 2 curQ = 0 case "S4": curSize = 2 diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 06435b4582..cf80f876b3 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -135,6 +135,11 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VLD1.P 64(R1), [V5.B16, V6.B16, V7.B16, V8.B16] // 2520df4c VST1.P [V4.S4, V5.S4], 32(R1) // 24a89f4c VST1 [V0.S4, V1.S4], (R0) // 00a8004c + VLD1 (R30), [V15.S2, V16.S2] // cfab400c + VLD1.P 24(R30), [V3.S2,V4.S2,V5.S2] // c36bdf0c + VST1.P [V24.S2], 8(R2) // 58789f0c + VST1 [V29.S2, V30.S2], (R29) // bdab000c + VST1 [V14.H4, V15.H4, V16.H4], (R27) // 6e67000c VMOVS V20, (R0) // 140000bd VMOVS.P V20, 4(R0) // 144400bc VMOVS.W V20, 4(R0) // 144c00bc -- 2.50.0